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SFD45N03L Datasheet

  • SFD45N03L

  • Logic N-Channel MOSFET

  • 1064.13KB

  • 7頁(yè)

  • ETC

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SemiWell
Semiconductor
SFD45N03L
Logic N-Channel MOSFET
Features
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Low R
DS
(on) (0.018鈩?)@V
GS
=10V
Low Gate Charge (Typical 17.5nC)
Low Crss (Typical 110pF)
Improved dv/dt Capability
100% Avalanche Tested
Maximum Junction Temperature Range (150擄C)
Symbol
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2. Drain
1. Gate
鈼€
鈼?/div>
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3. Source
General Description
This Power MOSFET is produced using SemiWell鈥檚 advanced
planar stripe, DMOS technology. This latest technology has been
especially designed to minimize on-state resistance, have a low
gate charge with superior switching performance, and rugged
avalanche characteristics. This Power MOSFET is well suited
for synchronous DC-DC Converters and Power Management in
portable and battery operated products.
D-PACK (TO-252)
2
1
3
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GS
E
AS
dv/dt
P
D
T
STG,
T
J
T
L
Drain to Source Voltage
Continuous Drain Current(@T
C
= 25
擄C)
Continuous Drain Current(@T
C
= 100
擄C)
Drain Current Pulsed
Gate to Source Voltage
Single Pulsed Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation(@T
A
= 25 擄C)
Total Power Dissipation(@T
C
= 25 擄C)
Derating Factor above 25 擄C
Operating Junction Temperature & Storage Temperature
Maximum Lead Temperature for soldering purpose,
1/8 from Case for 5 seconds.
(Note 2)
(Note 3)
(Note 1)
Parameter
Value
30
37
24
148
Units
V
A
A
A
V
mJ
V/ns
W
W
W/擄C
擄C
擄C
鹵
20
220
7.0
2.5
45
0.36
- 55 ~ 150
300
Thermal Characteristics
Symbol
R
胃JC
R
胃JA
R
胃JA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
Value
Min.
-
-
-
Typ.
-
-
-
Max.
2.78
50
110
Units
擄C/W
擄C/W
擄C/W
* When mounted on the minimum pad size recommended (PCB Mount)
September, 2002. Rev. 0.
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
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