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SDA9254-2 Datasheet

  • SDA9254-2

  • 2.6 MBit Dynamic Sequential Access Memory for Television App...

  • 32頁(yè)

  • INFINEON   INFINEON

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2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM) with
On-chip Noise Reduction Filter
Preliminary Data
Features
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SDA 9254-2
CMOS IC
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Stores a complete video field (4:1:1)
On chip adaptive recursive noise reduction filter (4:1:1)
4 noise reduction classes selectable
Special noise reduction mode for 4:2:2 applications
212
脳
64
脳
16
脳
12-bit organization
Triple port architecture
One 16
脳
12-bit input shift register
Two 16
脳
12-bit output shift registers
Shift registers independently and simultaneously
accessible (one output shift register is used internally for
noise reduction filtering)
Continuous data flow even at maximum speed
40-MHz shift rate - 0.96-Gbit/s total data rate
All inputs and outputs TTL-compatible
Tristate outputs
Random access of groups of 16
脳
12 bits for a wide range
of applications
Refresh-free operation possible
5 V
鹵
10 % power supply
0 鈥?70
擄C
operating temperature range
Low power dissipation: 700 mW active, 28 mW standby
Suitable for all common TV standards
Allows flicker and noise reduction simultaneously
with only one field memory
Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
P-MQFP-64-1
Type
SDA 9254-2
Ordering Code
on request
Package
P-MQFP-64-1
Semiconductor Group
1
1998-01-16

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