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SDA5649X Datasheet

  • SDA5649X

  • Expanded Decoder for Program Delivery Control and Video Prog...

  • 26頁

  • INFINEON   INFINEON

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Expanded Decoder for Program Delivery
Control and Video Program System
EPDC / VPS Decoder
SDA 5649
SDA 5649X
CMOS IC
Features
q
Single-chip receiver for PDC data, broadcast either
q
q
q
q
q
q
q
q
q
q
q
q
鈥?in Broadcast Data Service Packet (BDSP) 8/30/2
according to CCIR teletext system B, or
鈥?in dedicated line no. 16 of the vertical blanking interval
(VPS)
Reception of Unified Date and Time (UDT), Network
Identification code (NIC), and Short Program Label (SPL)
broadcast in BDSP 8/30/1
Reception of bytes no.38 through 45 of teletext header row
containing clock time
Low external components count
On-chip data and sync slicer
I
2
C-Bus interface for communication with external
microcontroller
Selection of PDC/VPS operating mode software controlled
by
I
2
C-Bus register
Pin and software compatible to PDC/VPS Decoder
SDA 5648
Supply voltage: 5 V
鹵
10 %
Video input signal level: 0.7 Vpp to 1.4 Vpp
Technology: CMOS
Package: P-DIP-14-3 and P-DSO-20-1
Operating temperature range: 0 to 70
擄C
Ordering Code
Q67100-H5156
Q67106-H5157
P-DIP-14-3
P-DSO-20-1
Type
SDA 5649
SDA 5649X
Functional Description
Package
P-DIP-14-3
P-DSO-20-1 Tape & Reel
The CMOS circuit SDA 5649 is intended for use in video cassette recorders to retrieve control data
of the PDC system from the data lines broadcast during the vertical blanking interval of a standard
video signal.
The SDA 5649 is devised to handle PDC data transported either in Broadcast Data Service Packet
(BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data
line no. 16 in the case of VPS.
Semiconductor Group
44
12.94

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