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SCANSTA101 Datasheet

  • SCANSTA101

  • Low Voltage IEEE 1149.1 STA Master

  • 31頁

  • NSC

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SCANSTA101 Low Voltage IEEE 1149.1 STA Master
October 2002
SCANSTA101
Low Voltage IEEE 1149.1 STA Master
General Description
The SCANSTA101 is designed to function as a test master
for a IEEE 1149.1 test system. The minimal requirements to
create a tester are a microcomputer (uP, RAM/ROM, clock,
etc.), SCANEASE r2.0 software, and a STA101.
The SCANSTA101 is an enhanced version of, and replace-
ment for, the SCANPSC100. The additional features of the
STA101 further allow it to offload some of the processor
overhead while remaining flexible. The device architecture
supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility
will allow it to adapt to any changes that may occur in 1532
and support yet unknown variants.
The SCANSTA101 is useful in improving vector throughput
when applying serial vectors to system test circuitry and
reduces the software overhead that is associated with ap-
plying serial patterns with a parallel processor. The SCAN-
STA101 features a generic Parallel Processor Interface
(PPI) which operates by serializing data from the parallel bus
for shifting through the chain of 1149.1 compliant compo-
nents (i.e., scan chain). Writes can be controlled either by
wait states or the DTACK line. Handshaking is accomplished
with either polling or interrupts.
Features
n
Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
n
Supported by National鈥檚 SCAN Ease (Embedded
Application Software Enabler) Software Rev 2.0
n
Available as a Silicon Device and Intellectual Property
(IP) model for embedding into VLSI devices
n
Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n
16-bit Data Interface (IP scalable to 32-bit)
n
2Kx32 bit dual-port memory addressing for access by
the PPI or the 1149.1 master
n
Load-on-the-fly (LotF) and Preload operating modes
supported
n
On-Board Sequencer allows multi-vector operations
such as those required to load data into an FPGA
n
On-Board Compares support TDI validation against
preloaded expected data
n
32-bit Linear Feedback Shift Register (LFSR) at the Test
Data In (TDI) port
n
State, Shift, and BIST macros allow predetermined TMS
sequences to be utilized
n
Operates at 3.3v supply voltages w/ 5V tolerant I/O
n
Outputs support Power-Down TRI-STATE mode.
SCANSTA101 Architecture
10121502
FIGURE 1.
漏 2002 National Semiconductor Corporation
DS101215
www.national.com

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