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SCAN12100 Datasheet

  • SCAN12100

  • 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Prec...

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SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes
November 2006
SCAN12100
1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and
Precision Delay Calibration Measurement
General Description
The SCAN12100 is a 1228.8 and 614.4 Mbps serializer/de-
seralizer (SerDes) for high-speed bidirectional serial data
transmission over FR-4 printed circuit board backplanes, bal-
anced cables, and optical fiber. The SCAN12100 integrates
precision delay calibration measurement (DCM) circuitry that
measures link delay components to better than 鹵 800 ps ac-
curacy.
The SCAN12100 features independent transmit and receive
PLLs, on-chip oscillator, and intelligent clock management
circuitry to automatically perform remote radio head synchro-
nization and reduce the cost and complexity of external clock
networks.
The SCAN12100 is programmable though an MDIO interface
as well as through pins, featuring configurable transmitter de-
emphasis, receiver equalization, speed rate selection, inter-
nal pattern generation/verification, and loop back modes. In
addition to at-speed BIST, the SCAN12100 includes IEEE
1149.1 and 1149.6 testability.
Note: For a full SCAN12100 datasheet please contact
your local National Semiconductor representitive
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DCM also measures chip and other delays to
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鹵 1200 ps
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accuracy
Deterministic chip latency
Automatic receiver lock and RE synchronization without
reference clock or external crystal
Independent transmit and receive PLLs for seamless RE
synchronization
Low noise recovered clock output
Requires no jitter cleaning in single-hop applications
>8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV
CDM
Hot plug protection
LOS, LOF, 8b/10b line code violation, comma, and
receiver PLL lock reporting
Programmable hyperframe length and start of hyperframe
character
Programmable transmit de-emphasis and receive
equalization with on-chip termination
Advanced testability features
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IEEE 1149.1 and 1149.6
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At-speed BIST pattern generator/verifier
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Multiple loopback modes
1.8V or 3.3V compatible parallel bus interface
100-pin TQFP package with exposed dap
Industrial 鈥?0 to +85擄 C temperature range
Features
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Exceeds LV and HV CPRI voltage and jitter requirements
1228.8, and 614.4 Mbps operation
Pin and package compatibility with the SCAN25100
Integrated delay calibration measurement (DCM) directly
measures T14 and Toffset delays to
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鹵 800 ps
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Block Diagram
20209542
漏 2006 National Semiconductor Corporation
202095
www.national.com

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