CDP1802AC/3
March 1997
High-Reliability CMOS 8-Bit Microprocessor
Description
The CDP1802A/3 High
-
Reliability LSI CMOS 8
-
bit register
oriented Central
-
Processing Unit (CPU) is designed for use
as a general purpose computing or control element in a wide
range of stored
-
program systems or products.
The CDP1802A/3 includes all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to facili-
tate system design.
The 1800 Series Architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum 鏗俥xibility and minimum cost can be
realized. The 1800 Series CPU also provides a synchronous
interface to memories and external controllers for I/O devices,
and minimizes the cost of interface controllers. Further, the I/O
interface is capable of supporting devices operating in polled,
interrupt
-
driven, or direct memory
-
access modes.
The CDP1802AC/3 is functionally identical to its predeces-
sor, the CDP1802. The 鈥淎鈥?version includes some perfor-
mance enhancements and can be used as a direct
replacement in systems using the CDP1802.
This type is supplied in 40 lead dual
-
in
-
line sidebrazed
ceramic packages (D suf鏗亁).
Features
鈥?For Use In Aerospace, Military, and Critical Industrial
Equipment
鈥?Minimum Instruction Fetch
-
Execute Time of 4.5碌s
(Maximum Clock Frequency of 3.6MHz) at V
DD
= 5V, T
A
= +25
o
C
鈥?Operation Over the Full Military
Temperature Range . . . . . . . . . . . . . . . -55
o
C to +125
o
C
鈥?Any Combination of Standard RAM and ROM Up to
65,536 Bytes
鈥?8鈥揃it Parallel Organization With Bidirectional Data
Bus and Multiplexed Address Bus
鈥?16 x 16 Matrix of Registers for Use as Multiple Pro-
gram Counters, Data Pointers, or Data Registers
鈥?On-Chip DMA, Interrupt, and Flag Inputs
鈥?High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V
DD
[ /Title
(CDP1
802AC
/3)
/Sub-
ject
(High-
Reli-
ability
CMOS
8-Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
8-bit
micro-
proces-
sors, 8
bit
micro-
proces-
sors,
periph-
erals)
/Cre-
ator ()
/DOCI
NFO
pdf-
mark
Ordering Information
PACKAGE
SBDIP
TEMP. RANGE
(
o
C)
-55 to 125
5V
-
3.2MHz
CDP1802ACD3
PKG
NO.
D40.6
Pinout
CDP1802AC/3 (SBDIP)
TOP VIEW
CLOCK
WAIT
CLEAR
Q
SC1
SC0
MRD
BUS 7
BUS 6
1
2
3
4
5
6
7
8
9
40 V
DD
39 XTAL
38 DMA IN
37 DMA OUT
36 INTERRUPT
35 MWR
34 TPA
33 TPB
32 MA7
31 MA6
30 MA5
29 MA4
28 MA3
27 MA2
26 MA1
25 MA0
24 EF1
23 EF2
22 EF3
21 EF4
BUS 5 10
BUS 4 11
BUS 3 12
BUS 2 13
BUS 1 14
BUS 0 15
V
CC
16
N2 17
N1 18
N0 19
V
SS
20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
1441.2
3-30
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