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SAA32M4 Datasheet

  • SAA32M4

  • DOUBLE DATA RATE (DDR) SDRAM

  • 256.33KB

  • 13頁

  • ETC

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128Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
鈥?/div>
PC1600 and PC2100 compatible
鈥?/div>
VDD = +2.5V 鹵0.2V, VDDQ = +2.5V 鹵0.2V
鈥?/div>
Bi-directional data strobe (DQS) transmitted/ received with
data, i.e., source-synchronous data capture (x16 has two 鈥?/div>
one per byte)
鈥?/div>
Internal, pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
鈥?/div>
Differential clock inputs (CK and CK#)
鈥?/div>
Commands entered on each positive CK edge
鈥?/div>
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
鈥?/div>
DLL to align DQ and DQS transitions with CK
鈥?/div>
Four internal banks for concurrent operation
鈥?/div>
Data mask (DM) for masking write data (x16 has two 鈥?/div>
one per byte)
鈥?/div>
Programmable burst lengths: 2, 4, or 8
鈥?/div>
Auto precharge option
鈥?/div>
Auto Refresh
鈥?/div>
Longer lead TSOP for improved reliability (OCPL)
鈥?/div>
2.5V I/O (SSTL_2 compatible)
Timing 鈥?Cycle Time
7.5ns @ CL = 2.5 (PC2100)
10ns @ CL = 2.5 (PC1600)
Part number example:
(For part numbers prior to December
2004, refer to
page 13
for decoding.)
-75A
-8A
SAA16M8T95AV4TL-75A
Options:
Family
SpecTek Memory
Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
Design ID
DDR 128 Megabit Design
(Call SpecTek Sales for details on
availability of 鈥渪鈥?placeholders)
Voltage and refresh
2.5V, Auto Refresh
2.5V, Self or Auto Refresh
Plastic Package 鈥?OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
Designation:
SAA
32M4
16M8
8M16
Yx6x
V4
R4
TL
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
1
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
漏
2001, 2002, 2004 SpecTek

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