Part Number - S4804CBI41
Product Brief Version 2.0 - January 2002
RHINE
Features
PRODUCT BRIEF
OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER
The S4804 is a highly-integrated VLSI device that provides
full-duplex mapping of packets or ATM cells to SONET/SDH
payloads. It provides support for both uni-directional and
bi-directional rings.
The S4804 provides full section, line, and path overhead
processing, and supports framing, scrambling/descrambling,
alarm signal insertion/detection, and bit-interleaved parity
(B1/B2/B3) processing.
The S4804 is SONET/SDH standards compliant with Bellcore
GR-253, ITU G.707, ITU-T 432.1, ANSI T1.105 -1995, and
IETF RFCs 1619/1661/1662/2615.
A general purpose 8-bit or 16-bit microprocessor interface is
provided for control and monitoring. The interface supports
both Intel
TM
and Motorola
TM
type microprocessors, and is
capable of operating in either an interrupt-driven or
polled-mode configuration. In addition, a standard 5 signal
IEEE 1149.1 JTAG Test Port is provided for Boundary Scan
test purposes.
鈥?Provides a SONET/SDH STS-48/STM-16, 4 STS-12/STM-
4, or 16 STS-3/STM-1 line interfaces.
鈥?STS-48/STM-16 data stream supports a single STS-48c/
AU-4-16c, or any valid combination of STS-12c/AU-4-4c
and/or STS-3c/AU-4 SONET/SDH payloads.
鈥?Each STS-12/STM-4 data stream supports a single STS-
12c/AU-4-4c or 4 STS-3c/AU-4 SONET/SDH payloads.
鈥?Each STS-3/STM-1 data stream supports a single
STS-3c/AU-4 SONET/SDH payload.
鈥?Supports mixed STS-3 / STS-12 line rates
鈥?Provides full-duplex mapping of ATM cells or packets in
each payload tributary.
鈥?Supports termination of mixed ATM and POS tributaries.
鈥?Terminates/generates SONET/SDH section, line, and path
layers with transport/section E1, E2, F1, and DCC over-
head interfaces in both transmit and receive directions.
鈥?APS port to support protection-switching configurations
between two RHINE devices.
鈥?16-bit, bus interface at 155 MHz for STS-48/STM-16 mode,
or serial interfaces operating at 622/155 MHz for STS-12/3
(STM-4/1) modes on the line side.
鈥?32-bit, parallel interface (FlexBus-3
TM
) operating at 100
MHz on the system side.
鈥?.25 micron, 2.5V core, and 3.3V tolerant I/O.
鈥?Packaged in a 624 Pin CBGA.
Applications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
ATM switches
Packet over SONET Routers and Switches
SONET/SDH Add Drop Multiplexers, Terminal
Multiplexers, and Digital Cross Connects
Test equipment
S4804CBI Block Diagram
APS_DAT_IN[0:31]
APS_CLK_IN[3:0]
TX_TOH_FRAME
TX_RING_DATA
SYNCMODE
RSTB
INTB
D[15:0]
ADDR[13:0]
CSN
WRB(RWB)
RDB(DSB)
RDYB(DTACKB)
BUSMODE
APS_INTB
TX_TOH_DAT
TX_TOH_CLK
UPCLK
TX_ERR[1:4]
TX_EOP[1:4]
TX_LBYTE[1:0]
TX_SYS_DAT[31:0]
TX_ADR[4:0]
TX_CLK[1:4]
TX_PRTY[1:4]
TX_ENB[1:4]
TX_SOC/P[1:4]
TX_CLAV_PDA[1:4]
TX_CLK_OUT[1:4]
RX_SYS_DAT[31:0]
RX_ADR[4:0]
RX_CLK[1:4]
RX_PRTY[1:4]
RX_ENB[1:4]
RX_SOC/P[1:4]
RX_CLAV_PDA[1:4]
RX_DV[1:4]
RX_LBYTE[1:0]
RX_EOP[1:4]
RX_ERR[1:4]
RX_CLK_OUT[1:4}
Production Release Information
- The information con-
tained in this document is about a product in its fully tested
and characterized phase. All features described herein are
supported. Contact AMCC for updates to this document and
the latest product status.
TX_SONETCLK_OUT_155_622
TX
TOH INSERT
SPE/VC
GEN.
MICROPROCESSOR I/F
TX ATM/HDLC
x16
PROC w/
(X
43
+ 1) SCRMBL
POH
MON.
x16
x16
LINE SIDE INTERFACE
TX_SONETCLK_OUT_155
TX_DATA[15:0]
TX_SONETCLK_IN
TX_FRAME_IN
RX_DATA[15:0]
RX_SONETCLK[1:16]
RX_LOSEXT[1:16]
RX_REF_CLK_OUT
FRAMER
x16
x16
RX
FRAMER
x16
TOH
MON.
x16
Ptr
Proc
x16
(X
43
RX ATM/HDLC
x16
PROC w/
+ 1) DeSCRMBL
Ptr
Intrp
x16
RX ATM/
HDLC
CNTRS
x16
TOH EXTRACT
GPIO/LED REG
JTAG PORT
RX
FIFO
x16
TRTSB
TS_EN
APS_DAT_OUT[0:31]
RX_TOH_DAT
RX_TOH_CLK
APS_CLK_OUT
RX_RING_DATA
TDO
RX_TOH_FRAME
RX_ALARM_OUT[1:16]
AMCC
GPIO[7:0]
TDI
TCK
TMS
UTOPIA-3 or FlexBus
TM
INTERFACE
TX
FIFO
1
2
