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RTL8139C_PLUS Datasheet

  • RTL8139C_PLUS

  • RTL8139C_Plus Specification

  • 100頁

  • ETC

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RTL8139C(L)+
REALTEK 3.3V SINGLE CHIP
FAST ETHERNET CONTROLLER
WITH POWER MANAGEMENT
RTL8139C(L)+
1. Features........................................................................ 3
2. General Description .................................................... 4
3. Block Diagram............................................................. 5
4. Pin Assignments .......................................................... 6
5. Pin Descriptions .......................................................... 7
5.1 Power Management/Isolation Interface ................. 7
5.2 PCI Interface .......................................................... 8
5.3 FLASH/BootPROM/EEPROM/MII Interface ..... 10
5.4 Power Pins ........................................................... 11
5.5 LED Interface....................................................... 11
5.6 Attachment Unit Interface.................................... 12
5.7 Test and Other Pins .............................................. 12
6. Register Descriptions ................................................ 13
6.1 Receive Status Register in Rx Packet Header ...... 15
6.2 Transmit Status Register ...................................... 16
6.3 Dump Tally Counter Command Register (DTCCR)... 17
6.4 ERSR: Early Rx Status Register .......................... 18
6.5 Command Register............................................... 18
6.6 Interrupt Mask Register ....................................... 19
6.7 Interrupt Status Register....................................... 20
6.8 Transmit Configuration Register.......................... 21
6.9 Receive Configuration Register ........................... 22
6.10 9346CR: 93C46 (93C56) Command Register ... 25
6.11 Configuration Register 0 (CONFIG 0) .............. 25
6.12 Configuration Register 1 (CONFIG 1) .............. 26
6.13 Media Status Register ........................................ 27
6.14 Configuration Register3 (CONFIG 3) ............... 28
6.15 Configuration Register4 (CONFIG 4) ............... 29
6.16 Multiple Interrupt Select Register ...................... 30
6.17 PCI Revision ID ................................................. 30
6.18 Transmit Status of All Descriptors Register (TSAD).. 30
6.19 Basic Mode Control Register ............................. 31
6.20 Basic Mode Status Register ............................... 32
6.21 Auto-negotiation Advertisement Register.......... 33
6.22 Auto-Negotiation Link Partner Ability Register ... 34
6.23 Auto-negotiation Expansion Register ................ 34
6.24 Disconnect Counter............................................ 35
6.25 False Carrier Sense Counter............................... 35
6.26 NWay Test Register ........................................... 35
6.27 RX_ER Counter ................................................. 35
6.28 CS Configuration Register ................................. 36
6.29 Low Address of a Tx Descriptor with Tx DMA Ok 36
6.30 Flash Memory Read/Write Register (FLASH) .. 36
6.31 Configuration Register 5 (Config5) ................... 37
2001/12/06
1
6.32 Transmit Priority Polling Register (TPPoll) ...... 38
6.33 C+ Command Register (C+CR) ......................... 38
6.34 Receive Descriptor Start Address Register (RDSAR)... 39
6.35 Early Transmit Threshold Register (ETThR) .... 39
6.36 Function Event Register..................................... 40
6.37 Function Event Mask Register........................... 41
6.38 Function Present State Register ......................... 42
6.39 Function Force Event Register/MII Register ............. 43
7. EEPROM Contents................................................... 44
7.1 Summary of EEPROM Registers......................... 46
7.2 Summary of EEPROM Power Management Registers 46
8. PCI Configuration Space Registers......................... 47
8.1 PCI Bus Interface................................................. 47
8.1.1 Byte Ordering ............................................... 47
8.1.2 Interrupt Control........................................... 47
8.1.3 Latency Timer .............................................. 47
8.1.4 32-Bit Data Operation .................................. 48
8.1.5 64-Bit Addressing ........................................ 48
8.2 Bus Operation ...................................................... 48
8.2.1 Target Read .................................................. 48
8.2.2 Target Write ................................................. 49
8.2.3 Master Read.................................................. 50
8.2.4 Master Write................................................. 51
8.2.5 Configuration Access ................................... 51
8.3 Packet Buffering .................................................. 51
8.3.1 Transmit Buffer Manager ............................. 52
8.3.2 Receive Buffer Manager .............................. 52
8.3.3 Packet Recognition....................................... 52
8.4 PCI Configuration Space Table ........................... 53
8.5 PCI Configuration Space Functions..................... 55
8.6 The Default Value After Power-on (RSTB asserted)...... 59
8.7 PCI Power Management Functions...................... 60
8.8 Vital Product Data (VPD) .................................... 62
9. Functional Description ............................................. 63
9.1 Transmit & Receive Operations in C mode ......... 63
9.1.1 Transmit........................................................ 63
9.1.2 Receive ......................................................... 63
9.2 Transmit & Receive Operations in C+ mode ....... 63
9.2.1 Transmit........................................................ 64
9.2.2 Receive ......................................................... 70
9.3 Line Quality Monitor ........................................... 73
9.4 Clock Recovery Module ...................................... 73
9.5 Loopback Operation............................................. 73
9.6 Tx Encapsulation with the Internal PHYceiver............ 73
Rev.1.5

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