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RNA50C27AUS

CMOS System-Reset IC

REJ03D0834-0100

Preliminary

Rev.1.00

Apr 10, 2006

Description

This IC facilitates complicated power-on and power-monitoring resets of microcomputers that require the 3.3-V and

1.8-V dual power supplies. It also facilitates change of delay time of reset signal by externally setting resistance and

capacity for delay time. By employing complementary open-drain output, desired output such as open-drain output and

CMOS output can be obtained.

Functions

鈥?/div>

3.3-V detection voltage

Accuracy of 3.3-V detection voltage

Hysteresis of 3.3-V detection voltage

Open-drain/CMOS output

1.8-V PMOS drive output

Ultra-small SSOP-8 package

: 2.7 V

:

鹵1.0%

: 5% Typ.

Block Diagram

MR

8

VDD33 1

鈥?/div>

+

CRext

7

2

RESP

Delay

3

RESN

Vref

VDD18 6

5 SWG

GND 4

Rev.1.00 Apr 10, 2006 page 1 of 7

型號

版本

描述

廠商

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RNA50C27AUS Datasheet

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