鈥?/div>
26dB small signal gain
26.5dBm output power @ 1dB compression
2.5% EVM at 18dBm modulated output power
3.5% EVM at 19dBm modulated output power
3.3V single positive supply operation
Two power saving shutdown options (bias and logic
control)
Integrated power detector with 20dB dynamic range
Low profile 16 pin 3 x 3 x 0.9 mm leadless package
Internally matched to 50
鈩?/div>
and DC blocked RF input/
output
Optimized for use in 802.11b/g applications
Device
Functional Block Diagram
VDET REF
VDET
VM12
VC2
16
15
14
13
Pin
1
2
3
12
Description
V
L
(logic)
RF IN
RF IN
N/C
VC1
N/C
N/C
N/C
N/C
RF OUT
RF OUT
N/C
VC2
VDET
VDET REF
VM12
V
L
1
BIAS
VOLTAGE
DETECTOR
N/C
RF IN
2
INPUT
MATCH
INT STG
MATCH
OUTPUT
MATCH
11
RF OUT
4
5
6
7
8
9
10
11
12
13
14
15
16
RF IN
3
10
RF OUT
N/C
4
9
N/C
5
6
7
8
N/C
N/C
VC1
N/C
Backside Ground
漏2004 Fairchild Semiconductor Corporation
RMPA2453 Rev. D
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