applications. The 2 stage PAM is internally matched to 50
鈩?/div>
to minimize the use of external components and features a
low-power mode to reduce standby current and DC power
consumption during peak phone usage. High power-added
efficiency and excellent linearity are achieved using our
Heterojunction Bipolar Transistor (HBT) process.
Features
鈥?Single positive-supply operation with low power and
shutdown modes
鈥?39% CDMA efficiency at +28dBm average output power
鈥?53% AMPS mode efficiency at +31dBm output power
鈥?Compact LCC package ( 4.0 X 4.0 x 1.5 mm)
鈥?Internally matched to 50
鈩?/div>
and DC blocked RF input/
output
鈥?Meets CDMA2000-1XRTT performance requirements
Device
Functional Block Diagram
PA MODULE
Vcc1
(5)
COLLECTOR
BIAS 1
GND
(3, 7, 9,10,11)
INTERSTAGE
MATCH
INPUT
MATCHING
NETWORK
OUTPUT
MATCHING
NETWORK
RF IN
(4)
INPUT
STAGE
INPUT STAGE
BIAS
MMIC
OUTPUT
STAGE
OUTPUT STAGE
BIAS
RF OUT
(8)
VCC=3.4V (nom)
VREF=2.85V (nom)
824-849 MHz
50鈩?I/O
Vref
(1)
BIAS CONTROL
COLLECTOR
BIAS 2
Vcc2
(6)
Vmode (2)
漏2004 Fairchild Semiconductor Corporation
RMPA0959 Rev. D
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