鈥?/div>
Specialized DSP integer Multiply-
Accumulate instructions
(MAD/MADU), and three-operand
Multiply instruction (MUL)
I and D Test/Break-point (Watch)
registers for emulation and debug
Performance counter for system
and software tuning and debug
鈥?/div>
PACKAGING
鈥?/div>
鈥?/div>
Fully Static 0.13碌 CMOS design
with dynamic power down logic
304 pin TBGA package, 31x31 mm
鈥?/div>
DEVELOPMENT TOOLS
鈥?Operating Systems:
鈥?/div>
Linux by MontaVista and Red Hat
鈥?/div>
VxWorks by Wind River Systems
鈥?/div>
Nucleus by Accelerated Technology
鈥?/div>
Neutrino by QNX Software Systems
鈥?Compiler Suites
鈥?/div>
Algorithmics
鈥?/div>
Green Hills Software
鈥?/div>
BLOCK DIAGRAM
64-bit Integer Unit
Dual-Issue Superscalar
Integer Multiplier
System Control
PC Unit
64-bit FP Unit
Double/Single IEEE754
Instr. Dispatch
I-Cache
16KB, 4-way, lockable
MMU
Fully Assoc., 48 or 64 Entry
D-Cache
16KB, 4-way, lockable
Bus Interface Unit
L3 Cache Control
System Cache (L2)
Int Ctlr
256KB, 4-way, lockable
64-bit
SysA /D Bus & L3 Ctr
NMI, INT9 鈥?INT0
PMC- 2011603(P1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2000
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