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RM5231A Datasheet

  • RM5231A

  • 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus

  • 2頁(yè)

  • PMC

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RM5231A/5261A
64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
FEATURES
鈥?Dual-Issue 64-bit Superscalar
architecture
鈥?/div>
High-performance 64-bit integer unit
鈥?/div>
High-throughput fully pipelined 64-
bit floating point unit (IEEE754)
鈥?High performance SysAD interface
鈥?/div>
32-bit or 64-bit multiplexed system
address/data bus for optimum
price/performance
鈥?/div>
Available with 32-bit or 64-bit
external bus interface
鈥?/div>
Supports fractional clock ratios
鈥?/div>
IEEE 1149.1 JTAG boundary scan
鈥?Integrated primary caches
鈥?/div>
32KB instruction - 2-way set
associative
鈥?/div>
32KB data - 2-way set associative
鈥?/div>
Virtually indexed, physically tagged
鈥?/div>
Write-back and write-through on
per-page basis
鈥?/div>
Pipeline restart on first double word
for data cache misses
鈥?64-bit MIPS instruction set architecture
鈥?/div>
Floating point multiply-add
instruction increases performance in
signal processing and graphics
applications
鈥?/div>
Conditional moves to reduce branch
frequency
鈥?/div>
Index address modes (register +
register)
鈥?Integrated memory management
鈥?/div>
Fully associative joint TLB (shared
by I and D transistors)
鈥?/div>
48 dual entries map 96 pages
鈥?/div>
Variable page size (4KB to 16MB)
鈥?Embedded application enhancements
鈥?/div>
Specialized DSP integer Multiply-
Accumulate instructions
(MAD/MADU) and 3 operand
Multiply instruction (MUL)
鈥?/div>
Instruction and Data cache locking
by set
鈥?/div>
Optional dedicated exception vector
for interrupts
Device
CPU
Frequency
(MHz)
I/D
Cache
32K/32K
32K/32K
External
Cache
Support
No
No
External Bus
Width
32-bit
64-bit
External Bus
Frequency
(MHz)
100
125
VccInt
(V)
1.65/1.8
1.65/1.8
VccIO
(V)
2.5/3.3
2.5/3.3
Package
128 QFP
208 QFP
RM5231A 250, 300, 350
RM5261A 250, 300, 350
BLOCK DIAGRAM
64-bit Integer unit
Dual-Issue
Superscalar
Integer Multiplier / Accum.
System Control
PC Unit
64-bit FP Unit
Double / Single
IEEE 754
Instr. Dispatch
I-Cache 32KB,
2-way, lockable
MMU 96 Pages,
(4KB 鈥?16 MB)
D-Cache 32KB, 2-
way, lockable
Bus Interface Unit
32-bit (5231A)
64-bit (5261A)
SysA / D Bus
Int Ctlr
NMI, INT5 鈥?INT0
PMC- 2010740 (R1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2000

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