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RM5231-150Q Datasheet

  • RM5231-150Q

  • 64-Bit Microprocessor

  • 20頁

  • ETC

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RM5231鈩?Microprocessor
with 32-Bit System Bus
Document Rev. 1.3
Date: 01/2000
FEATURES
鈥?Dual Issue superscalar microprocessor
鈥?/div>
150, 200, & 250 MHz operating frequencies
鈥?/div>
300 Dhrystone2.1 MIPS
鈥?System interface optimized for embedded applications
鈥?/div>
32-bit system interface lowers total system cost
鈥?/div>
High-performance write protocols maximize uncached write
bandwidth
鈥?/div>
Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
鈥?/div>
2.5V core with 3.3V IO鈥檚
鈥?/div>
IEEE 1149.1 JTAG boundary scan
鈥?Integrated on-chip caches
鈥?/div>
32KB instruction and 32KB data - 2 way set associative
鈥?/div>
Per set locking
鈥?/div>
Virtually indexed, physically tagged
鈥?/div>
Write-back and write-through on a per page basis
鈥?/div>
Pipeline restart on first doubleword for data cache misses
鈥?Integrated memory management unit
鈥?/div>
Fully associative joint TLB (shared by I and D translations)
鈥?/div>
48 dual entries map 96 pages
鈥?/div>
Variable page size (4KB to 16MB in 4x increments)
鈥?High-performance floating-point unit - up to 500 MFLOPS
鈥?/div>
Single cycle repeat rate for common single-precision opera-
tions and some double precision operations
鈥?/div>
Two cycle repeat rate for double-precision multiply and dou-
ble precision combined multiply-add operations
鈥?/div>
Single cycle repeat rate for single-precision combined multi-
ply-add operation
鈥?MIPS IV instruction set
鈥?/div>
Floating point multiply-add instruction increases perfor-
mance in signal processing and graphics applications
鈥?/div>
Conditional moves to reduce branch frequency
鈥?/div>
Index address modes (register + register)
鈥?Embedded application enhancements
鈥?/div>
Specialized DSP integer Multiply-Accumulate instructions
and 3-operand multiply instruction
鈥?/div>
I and D cache locking by set
鈥?/div>
Optional dedicated exception vector for interrupts
鈥?Fully static 0.25 micron CMOS design with power down logic
鈥?/div>
Standby reduced power mode with WAIT instruction
鈥?/div>
2.5V core with 3.3V I/O
鈥?128-pin Power-Quad 4 (QFP) package
BLOCK DIAGRAM
Primary Data Cache
2-way Set Associative
DTag
DTLB
ITag
ITLB
Primary Instruction Cache
2-way Set Associative
A/D Bus
Pad Bus
Store Buffer
Write Buffer
Read Buffer
Pad Buffer
Address Buffer
Instruction Dispatch Unit
FP
Instruction
Register
FP Bus
Integer Bus
Integer
Instruction
Register
D Bus
Floating-Point Control
Floating-Point
Load/Align
Floating-Point
Register File
Packer/Unpacker
Joint TLB
DVA
Load Aligner
Integer Address/Adder
System/Memory
Control
PC Incrementer
FA Bus
IVA
Shifter/Store Aligner
Logic Unit
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
Branch PC Adder
ITLB Virtual
Program Counter
DTLB Virtual
PLL/Clocks
Int Mult, Div, Madd
Quantum Effect Devices
www.qedinc.com
RM5231 Microprocessor, Document Rev. 1.3
Integer Control
Coprocessor 0
Integer Register File
1

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