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RL56CSMV/3 Datasheet

  • RL56CSMV/3

  • Telecomm/Datacomm

  • 14頁

  • ETC

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RL56CSMV/3 and RL56CSM/3
AnyPort鈩?Multi-Service Access Processor
The RL56CSMV/3 and RL56CSM/3 are members of the Conexant
鈩?/div>
AnyPort鈩?family of
multi-service access processors, and provide a complete solution to the transport of
multiple media types between circuit-switched remote access and a variety of back-end
networks (Table 1). AnyPort processors are ideally suited for the network infrastructures
resulting from the convergence of voice and data networking, addressing new
requirements such as Voice and Fax over packet networks, ISDN and Cellular Data, while
maintaining support of traditional PSTN Data/Fax needs.
Note:
RL56CSMV/3 and CSMV/3 refer to both RL56CSMV/3 and RL56CSM/3 except as
noted. Any reference to voice applies only to the RL56CSMV/3.
The CSMV/3 transcends existing modem solutions by providing a complete system
solution for multi-service remote access. The combined DSP/RISC architecture provides
an ideal engine to run Conexant鈥檚 extensive suite of field-proven modulations, echo
cancellers, voice coders, and communications protocols. In addition, performing
functions such as T.38, V.120, async-to-sync HDLC conversion for PPP, V.110, and
synchronous HDLC for PPP on ISDN connections, in the access processor allows system
designers to reduce system overhead and increase scalability.
The CSMV/3 is a low-power system providing three communication channels in a single
package. Powerful and downloadable DSP-based data pumps employ on-chip SRAM to
allow upgrades to future voice and communication modulation schemes. An advanced
RISC microcontroller manages three data pumps simultaneously. An innovative host
interface to the Multi-Service Access Processor system uses a shared SDRAM memory
to increase data throughput while reducing system cost and space. A programmable time
slot selection feature provides direct digital connection to a T1/E1/PRI framing device.
A 35mm BGA package houses the CSMV/3 with extra balls available for thermal vias to
minimize heat. A built-in phase lock loop (PLL) minimizes board noise while easing
design. A quick-wake, sleep mode further reduces the power of this +3.3V access
processor system.
Features
Generic
鈥?/div>
Three access channels in one package
鈥?/div>
+3.3V operation with +5V tolerant inputs
鈥?/div>
Downloadable controller firmware and data
pump code
鈥?/div>
Advanced RISC Machines (ARM) architecture
鈥?/div>
Low-power sleep mode with quick wake
鈥?/div>
Glueless interface to Bt8370 T1/E1/PRI framer
with time slot selection
鈥?/div>
Built-in phase lock loop (PLL)
Signaling
鈥?/div>
DTMF detection and generation
鈥?/div>
Multi-frequency tone support for legacy
network equipment (R1 and R2)
Data
鈥?/div>
Data modem modes
鈭?/div>
PSTN: ITU-T V.90, K56flex, K56Plus, V.34
(33.6 kbps), V.FC, V.32 bis, V.32, V.22 bis,
V.22A/B, V.23, and V.21; Bell 212A and 103
鈭?/div>
ISDN: 64/56 kbps ISDN Basic Rate Interface
B Channel HDLC control, or data pass-
through mode for HDLC processing
elsewhere in the central site system
鈥?/div>
Internal error correction and data compression
(ECC)
鈭?/div>
V.42 LAPM and MNP 2-4 error correction
鈭?/div>
V.42 bis and MNP 5 data compression
鈭?/div>
MNP 10EC鈩?enhanced cellular
鈥?/div>
Async/sync HDLC conversion
鈥?/div>
V.120 ISDN data
鈥?/div>
V.110 cellular data
鈥?/div>
LAP-B X.75
Voice (RL56CSMV/3 only)
鈥?/div>
Baseline configuration:
鈭?/div>
G.723.1 and G.723.1 Annex A
鈭?/div>
G.711
碌-law
and A-law
鈭?/div>
G.729 Annex A and Annex B
鈭?/div>
G.168 128 ms Network Echo Canceller
鈥?/div>
Patented robust jitter buffer
鈥?/div>
Voice API using Mailbox Messages
FAX
鈥?/div>
Fax modem send and receive rates up to 14.4 kbps
鈥?/div>
V.17, V.33, V.29, V.27 ter, and V.21 channel 2,
Group 3, T.30 protocol and Class 1, 2
supported
鈥?/div>
T.38 real-time fax protocol
Communications software-compatible
AT commands
Data Sheet
Preliminary
Doc. No. MD233
Rev. 2, July 9, 1999

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