P
Semiconductor Solutions for
H i g h S p e e d Co m m u n i c a t i o n s
and Fiber Optic Applications
The In鏗乶eon Resilient Ring Processor is a packet opti-
mized transport engine designed to enable the 鏗乺st
generation of Resilient Packet Rings (RPR) for metro-
politan area networks. Its feature-rich design supports
spatial reuse protocol (SRP) at speeds up to 10 Gbit/s.
It incorporates packet support for both POS and native
Ethernet with the 鏗俥xibility to transport across SONET,
DWDM or dark 鏗乥er. The In鏗乶eon Resilient Ring Proces-
sor is uniquely positioned to enable cost-effective resil-
iency and QoS for growing, high-speed IP networks.
R O D U C T
B
R I E F
Key Features
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High speed SRP MAC
Up to OC-192 (10 Gbit/s) throughput
Supports SRP, POS, Native Ethernet
1 MB low-priority transit buffer
32 KB high-priority transit buffer
Giant, runt and short packet filters
Supports IPS and topology discovery
899-pin Hyper BGA package
Specifications
Modes of Operation
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Dual ring mode
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Wrap mode
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Pass-through mode
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Transparent mode
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Passive and active sniffer modes
Operational Speeds
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OC-192
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OC-48
Packet Formats
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SRP
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Pseudo-SRP
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POS (in transparent mode)
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Native Ethernet
RX/TX Framer
Host Interface
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64-bits HSTL @200 MHz
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OIF SPI-4 Phase 1 compliant interface
Giant, runt and short packet filtering
with PM counters
Data and control parity bit checking
with PM counters
Traffic flow monitoring
Host-side leaky bucket rate limiters -
high/low priority
Data parity fault insertion for system
and software test
Counters for high/low priority
unicast/multicast packets and bytes
MATE Interface
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XGMII 10 gigabit interface
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4, 8-bit channels at 312.5 MHz
(10.0 Gbit/s total capacity)
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Automatic pass-through/wrap/
transparent mode communication
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Requires only 1 standard SERDES for
inter-board communication
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Loss of sync detection with
performance counters
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CRC detection
Rhea
Lookup / Statistics
CAM Functions
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1024 Double (source, destination or
both) address entries
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1024 Double address counters
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CAM S/W features: read/write/
probe/reset individual entries
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8 coarse multicast address filters
accept or reject on match
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Multicast accept/reject capability
for individual addresses
Transit Buffer
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Internal source and sink for usage
packets
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Internal 1 MB low and 32 KB high
priority buffers
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Counters for high/low priority
unicast/multicast packets and bytes
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Counters for min, max and average
delay in transit buffers
Microprocessor Interface
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16-bit, asynchronous interface, up to
100 MHz
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Multiple interrupt reporting
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Send and receive buffers for IPS and
topology packets
Electrical/Mechanical/Thermal
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1.5/1.8/3.3 V power supplies
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899-pin Hyper BGA Flip Chip
package
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-40 擄C to 85
擄C
operation
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~5.18 W
Other
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JTAG Compliant
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100 MHz or 200 MHz reference clock
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Hard and soft reset
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CRC generation and checking
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Extensive loopback features for
testing
R h ea
Resilient Ring Processor
OC-48 / OC-192 SRP MAC
N e v e r
s t o p
t h i n k i n g .
RESILIENTRINGPROCESSOR相關(guān)型號(hào)PDF文件下載
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