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RC32434-350BCI Datasheet

  • RC32434-350BCI

  • IDT TInterprise Integrated Communications Processor

  • 53頁

  • IDT

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IDT
TM
Interprise
TM
Integrated
Communications Processor
RC32434
Device Overview
The RC32434 is a member of the IDT鈩?Interprise鈩?family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
memory with minimal CPU intervention, using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32434 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
Features
x
32-bit CPU Core
鈥?MIPS32 instruction set
鈥?Cache Sizes: 8KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
鈥?16 dual-entry JTLB with variable page sizes
鈥?3-entry instruction TLB
鈥?3-entry data TLB
鈥?Max issue rate of one 32x16 multiply per clock
鈥?Max issue rate of one 32x32 multiply every other clock
鈥?CPU control with start, stop, and single stepping
鈥?Software breakpoints support
鈥?Hardware breakpoints on virtual addresses
鈥?ICE Interface that is compatible with v2.5 of the EJTAG Spec-
ification
PCI Interface
鈥?32-bit PCI revision 2.2 compliant
鈥?Supports host or satellite operation in both master and target
modes
鈥?Support for synchronous and asynchronous operation
鈥?PCI clock supports frequencies from 16 MHz to 66 MHz
鈥?PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
鈥?I
2
O 鈥渓ike鈥?PCI Messaging Unit
x
Ethernet Interface
鈥?10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
鈥?Supports MII or RMII PHY interface
鈥?Supports 64 entry hash table based multicast address filtering
鈥?512 byte transmit and receive FIFOs
鈥?Supports flow control functions outlined in IEEE Std. 802.3x-
1997
x
DDR Memory Controller
鈥?Supports up to 256MB of DDR SDRAM
鈥?1 chip select supporting 4 internal DDR banks
鈥?Supports a 16-bit wide data port using x8 or x16 bit wide DDR
SDRAM devices
鈥?Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR
SDRAM devices
鈥?Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
鈥?Automatic refresh generation
x
Block Diagram
MII/RMII
I
2
C Bus
MIPS-32
CPU Core
ICE
EJTAG
D. Cache
PMBus
Interrupt
Controller
:
:
1 Ethernet
10/100
Interface
MMU
I. Cache
3 Counter
Timers
IPBus
TM
I
2
C
Controller
DMA
Controller
DDR
(16-bit)
DDR
Controllers
Arbiter
Memory & I/O
Controller
Bus/System
Integrity
Monitor
1 UART
(16550)
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory &
Peripheral Bus (8-bit)
Serial Channel
GPIO Pins
SPI Bus
PCI Bus
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 53
錚?/div>
2005 Integrated Device Technology, Inc.
January 19, 2006
DSC 6214

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