音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

QS5LV919 Datasheet

  • QS5LV919

  • 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FIL...

  • 12頁

  • IDT

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FEATURES:
DESCRIPTION:
QS5LV919
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
3.3V operation
JEDEC compatible LVTTL level outputs
Clock inputs are 5V tolerant
< 300ps output skew, Q
0
鈥換
4
2xQ output, Q outputs,
Q
output, Q/2 output
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Functional equivalent to MC88LV915, IDT74FCT388915
Positive or negative edge synchronization (PE)
Balanced drive outputs 鹵24mA
160MHz maximum frequency (2xQ output)
Available in QSOP and PLCC packages
The QS5LV919 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to one of two reference clock inputs.
Eight outputs are available: 2xQ, Q
0
-Q
4
, Q
5
, Q/2. Careful layout and
design ensure < 300 ps skew between the Q
0
-Q
4
, and Q/2 outputs.
The QS5LV919 includes an internal RC filter which provides excellent
jitter characteristics and eliminates the need for external components.
Various combinations of feedback and a divide-by-2 in the VCO path
allow applications to be customized for linear VCO operation over a
wide range of input SYNC frequencies. The PLL can also be disabled
by the PLL_EN signal to allow low frequency or DC testing. The LOCK
output asserts to indicate when phase lock has been achieved. The
QS5LV919 is designed for use in high-performance workstations, multi-
board computers, networking hardware, and mainframe systems. Sev-
eral can be used in parallel or scattered throughout a system for guar-
anteed low skew, system-wide clock distribution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LO CK
SYNC
0
SYNC
1
O E/RST
0
0
1
PH A SE
DETECTO R
LOO P
FILTER
1
PE
FEEDBACK
PLL_EN
FREQ _SEL
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /
2
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
2xQ
INDUSTRIAL TEMPERATURE RANGE
1
c
2001
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JULY 2001
DSC-5820/3

QS5LV919相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！