鈥?/div>
5V operation
Five low noise CMOS level outputs
<500ps output skew, Q
0
鈥換
4
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Balanced drive outputs 鹵36mA
80MHz maximum frequency
Available in QSOP package
QS5935
DESCRIPTION
The QS5935 Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to a reference clock input. Five outputs are
available: Q
0
鈥換
4
. Careful layout and design ensure <500ps skew between
the Q
0
鈥換
4
. The QS5935 includes an internal RC filter which provides
excellent jitter characteristics and eliminates the need for external compo-
nents. The PLL can also be disabled by the PLL_EN signal to allow low
frequency or DC testing. The QS5935 is designed for use in cost sensitive
high-performance computing systems, workstations, multi-board comput-
ers, networking hardware, and mainframe systems. Several can be used
in parallel or scattered throughout a system for guaranteed low skew,
system-wide clock distribution networks. In the QSOP package, the QS5935
clock driver represents the best value in small form factor, high-performance
clock management products.
FUNCTIONAL BLOCK DIAGRAM
PLL_EN
/2
CLK_IN
PLL
FEEDBAC K
0
1
Q
0
Q
1
Q
2
Q
3
Q
4
OE/RST
INDUSTRIAL TEMPERATURE RANGE
1
c
2000
Integrated Device Technology, Inc.
JULY 2000
DSC-5816/-