鈥?/div>
5V operation
Low noise CMOS level outputs
< 500ps output skew, Q
0
鈥換
4
2xQ output, Q outputs,
Q
output, Q/2 output
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Functional equivalent to Motorola MC88915
Positive or negative edge synchronization (PE)
Balanced drive outputs 鹵36mA
160MHz maximum frequency (2xQ output)
Available in QSOP and PLCC packages
QS5919
DESCRIPTION
The QS5919 Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight outputs
are available: 2xQ, Q
0
-Q
4
, Q
5
, Q/2. Careful layout and design ensure
< 500ps skew between the Q
0
-Q
4
, and Q/2 outputs. The QS5919 includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5919 is designed for use in high-
performance workstations, multi-board computers, networking hard-
ware, and mainframe systems. Several can be used in parallel or
scattered throughout a system for guaranteed low skew, system-wide
clock distribution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LO CK
SYNC
0
SYNC
1
O E/RST
0
0
1
PH A S E
D ETEC TO R
LO O P
FIL TER
1
PE
FEE DBACK
PLL_E N
FREQ _SEL
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /
2
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
2xQ
INDUSTRIAL TEMPERATURE RANGE
1
c
2000
Integrated Device Technology, Inc.
JULY 2000
DSC-5823/-