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QS53806ASO Datasheet

  • QS53806ASO

  • Five Distributed-Output Clock Driver

  • 6頁

  • ETC

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QS53806/A
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
FEATURES
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JEDEC compatible LVTTL inputs and outputs
10 low skew clock outputs (inverting)
Monitor output
Clock inputs are 5V tolerant
Pinout and function compatible with QS5806
Input hysteresis for better noise margin
Guaranteed low skew
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0.6ns output skew (same bank)
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0.8ns output skew (different banks)
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1.5ns part-to-part skew
Std. and A speed grades
Available in QSOP and SOIC packages
QS53806/A
DESCRIPTION
The QS53806 clock driver/buffer circuit can be used for clock buffering
schemes where low skew is a key parameter. The QS53806 offers two
banks of five inverting outputs. Designed in IDT's proprietary CMOS
process, these devices provide low propagation delay buffering with on-
chip skew of 0.6ns for same-transition, same-bank signals.
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FUNCTIONAL BLOCK DIAGRAM
OE
A
5
IN
A
OA
5 -
OA
1
MO N
5
OB
5 -
OB
1
IN
B
OE
B
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
JULY 2000
DSC-5828/-

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