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QLUX2108-PT280C Datasheet

  • QLUX2108-PT280C

  • Telecommunication IC

  • 22頁

  • ETC

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QLUX2108-PT280C Device Data Sheet
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Utopia Level 2 Slave to Utopia Level 1 Master Bridge
1.0 Utopia Level 2/1 Bridge Core Features
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Implements an Utopia L2 Slave and Utopia L1 Master providing a solution to bridge
Utopia Level 1 Slave devices to a Level 2 Master
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Compliant with ATM-Forum af-phy-0039.000 (Level 2) and af-phy-0017.000 (Level 1)
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Implements 8-bit data busses
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Level 2 interface implements a single PHY using MPHY mode with direct status
indication
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Level 2 interface meets 50MHz performance offering up to 400Mbps cell rate transfers
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Level 1 interface meets 25MHz performance offering up to 200Mbps cell rate transfers
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Single chip solution for improved system integration
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Supports cell level transfer mode
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Cell and clock rate decoupling with on chip FIFOs
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Up to 2 KByte of on chip FIFO per data direction
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Integrated management interface and built-in errored cell discard
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ATM Cell size programmable via external pins from 16 to 128 bytes
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Level 2 MPHY address programmable via external pins
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Optional Utopia parity generation/checking enable/disable via external pin
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Built in JTAG port (IEEE1149 compliant)
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Simulation model available for system level verification (Contact Quicklogic for details)
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Solution also available as flexible Soft-IP core, delivered with a full device modelization
and verification testbenches
QLUX2108-PT280C Device Data Sheet
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