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QLUS3316-PQ208C Datasheet

  • QLUS3316-PQ208C

  • Telecommunication IC

  • 20頁(yè)

  • ETC

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QLUS3316-PQ208C Device Data Sheet
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Utopia Level 3 Slave Bridges
1.0 Utopia Level 3 (L3) Bridge Core Features
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Implements two Utopia L3 Slaves providing a solution to bridge Utopia Master devices
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Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)
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Meets 90MHz performance offering more than 1.4Gbps cell rate transfers
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Single chip solution for improved system integration
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Support cell level transfer mode, single PHY
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Cell and clock rate decoupling with on chip FIFOs
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Up to 1.5 KByte of on chip FIFO per data direction
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Integrated management interface and built-in errored cell discard
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ATM Cell size programmable via external pins from 16 to 128 bytes
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Optional Utopia parity generation/checking enable/disable via external pin
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Built in JTAG port (IEEE1149 compliant)
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Simulation model available for system level verification (Contact Quicklogic for details)
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Solution also available as flexible Soft-IP core, delivered with a full device modelization
and verification testbenches
QLUS3316-PQ208C Device Data Sheet
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