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QLUM3333-PT280C Datasheet

  • QLUM3333-PT280C

  • Telecommunication IC

  • 20頁

  • ETC

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QLUM3333-PT280C Device Datasheet
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Utopia Level 3 Master/Master Bridge
1.0 Utopia Level 3 (L3) Bridge Features
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Implements two Utopia L3 Masters providing a solution to bridge Utopia Slave devices
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Compliant with ATM-Forum af-phy-0136.000 (Utopia L3)
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Meets 104MHz performance offering up to 3.2Gbps cell rate transfers
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Single chip solution for improved system integration
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Support cell level transfer mode
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Cell and clock rate decoupling with on chip FIFOs
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Up to 1.5 KByte of on chip FIFO per data direction
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Integrated management interface and built-in errored cell discard
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ATM Cell size programmable via external pins from 16 to 128 bytes
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Optional Utopia parity generation/checking enable/disable via external pin
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Built in JTAG port (IEEE1149 compliant)
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Simulation model available for system level verification (Contact Quicklogic for details)
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Solution also available as flexible Soft-IP core, delivered with a full device modelization
and verification testbenches
QLUM3333-PT280C Device Data Sheet
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