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QLUM3216-PT280C Datasheet

  • QLUM3216-PT280C

  • Telecommunication IC

  • 22頁

  • ETC

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QLUM3216-PT280C Device Data Sheet
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Utopia Level 3 to Level 2 Master/Master Bridge
1.0 Utopia Level 3 to Level 2 Master Bridge Features
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Implements one Utopia L3 Master and one Utopia L2 Master providing a solution to
bridge Utopia Slave devices of different Levels
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Compliant with ATM-Forum af-phy-0039.000 (L2) and af-phy-0136.000 (L3)
specification
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Single chip solution for improved system integration
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Supports 16 Bit busses on both interfaces, single PHY
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Support for cell level transfer mode
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Meets 50MHz performance on Level 2 interface offering up to 800Mbps cell rate
transfers
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Cell and clock rate decoupling with on chip FIFOs
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Up to 1.5 KByte of on chip FIFO per data direction
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Integrated management interface and built-in errored cell discard
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ATM Cell size programmable via external pins from 16 to 128 bytes
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Optional Utopia parity generation/checking enable/disable via external pin
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Built in JTAG port (IEEE1149 compliant)
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Simulation model available for system level verification (Contact Quicklogic for details)
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Solution also available as flexible Soft-IP core, delivered with a full device modelization
and verification testbenches
QLUM3216-PT280C Device Data Sheet1
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