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QL80FC - QuickFC

TM

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QL80FC - QuickFC

F

EATURES

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D

UAL

P

ORT

SRAM

Dual Port SRAM

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ANSI Fibre Channel (FC) compatibility

Data rates up to 2.5 Gb/s supported

2.5Gb/s Simplex (200 MByte/s) or Duplex

(400 MByte/s) Mode

Compatible with standard SERDES components

32 bit synchronous FIFO system interface

Tx and Rx internal FIFO for system applications

without external FIFOs

Selectable 20-bit/10-bit encoded transmission

character interface to SERDES

8b/10b Encoding/Decoding

CRC Calculation and checking per FC standard

Fibre Channel Loss of Synchronization (LOS) state

machine

Support for arbitrated loops

IntraFrame idles support for proprietary links

鈥淩aw鈥?data path for the injection of encoding and

CRC errors into the bitsteam for use in testing link

error handling functions

3.3V operating voltage

3.3V CMOS I/O, 5.0V CMOS tolerant inputs

208 PQFP and 456 PBGA packages available

Features

22 blocks (total of 25,344 bits) of dual-port RAM

Configurable as RAM, ROM or FIFO

Can be configured as two internal FIFOs of up to

352 x 36 in size

Configurable RAM array sizes (by 2, 4, 9, 18)

<5ns access times, 160+Mhz FIFOs

H

IGH

S

PEED

C

USTOMIZABLE

L

OGIC

High Speed Customizable Logic

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Up to 269 customizable I/O pins

751 Logic cells

300 MHz 16-bit counters, 400 MHz Data paths

Mux-Based architecture; non-volatile technology

Completely customizable for any digital application

10 bit/20 bit

10 bit/20 bit

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Transmit

Fibre Channel ENDEC

Receive

IO Pins

Customizable

Logic Cells

Extended Features

Extended features that can be designed into the user

customizable logic:

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Fibre Channel Link Control State Machine (LCSM)

RRDY credit management for link flow control

Microprocessor interface to configure various link

modes

BIST functions support link bit error rate

measurements

RAM Blocks

22 Blocks (25K bits)

IO Pins

Fibre Channel Block Diagram

IO Pins

E

XTENDED

F

EATURES

1

Rev A

next

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