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QL8025 Datasheet

  • QL8025

  • LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM

  • 49頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

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1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O
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Up to 4,008 dedicated flip-flops
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Up to 55.3 K embedded RAM Bits
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Up to 313 I/O
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Up to 370 K system gates
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Multiple dedicated Low Skew Clock
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High drive input-only networks
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Quadrant-based segmentable clock networks
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User Programmable Phase Locked Loops
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Up to twenty-four 2,304 bit Dual Port High
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Up to 55,296 embedded RAM bits
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RAM/ROM/FIFO Wizard for automatic
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Configurable and cascadable
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High performance I/O cell with Tco< 3 ns
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Programmable Slew Rate Control
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Programmable I/O Standards:
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LVTTL, LVCMOS, LVCMOS18, PCI,
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Embeded Computational Units
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Independent I/O Banks capable of
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I/O Register Configurations: Input,
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