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4 194 304 words by 32-bit organization
(alternative 8 388 608 words by 16-bit)
Fast access and cycle time
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
Fast page mode capability
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
Single + 5 V (鹵 10 %) supply
Low power dissipation
max. 4840 mW active
(HYM 324020S/GS-60)
max. 4400 mW active
(HYM 324020S/GS-70)
CMOS 鈥?44 mW standby
TTL 鈥?88 mW standby
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CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
8 decoupling capacitors mounted on
substrate
All inputs, outputs and clocks fully TTL
compatible
72 pin Single in-Line Memory Module with
22.86 mm (900 mil) height
Utilizes eight 4Mx4-DRAMs in 300mil wide
SOJ-packages
2048 refresh cycles / 32 ms
Tin-Lead contact pads (S - version)
Gold contact pads (GS - version)
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Ordering Information
Type
HYM 324020S-60
HYM 324020S-70
HYM 324020GS-60
HYM 324020GS-70
Ordering Code
Q67100-Q979
Q67100-Q980
Q67100-Q2005
on request
Package
L-SIM-72-12
L-SIM-72-12
L-SIM-72-12
L-SIM-72-12
Description
DRAM Module
(access time 60 ns)
DRAM Module
(access time 70 ns)
DRAM Module
(access time 60 ns)
DRAM Module
(access time 70 ns)
Semiconductor Group
571
09.94
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Q67100-Q980相關(guān)型號(hào)PDF文件下載
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型號(hào)
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