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Q67100-Q2178 Datasheet

  • Q67100-Q2178

  • 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM M...

  • 77.99KB

  • 14頁(yè)

  • INFINEON   INFINEON

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3.3V 1M
脳
64-Bit EDO-DRAM Module
3.3V 1M x 72-Bit EDO-DRAM Module
168pin unbuffered DIMM Module
with serial presence detect
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HYM64V1005GU-50/-60
HYM72V1005GU-50/-60
168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module
for PC main memory applications
1 bank 1M x 64, 1M x 72 organisation
Optimized for byte-write non-parity or ECC applications
Extended Data Out (EDO)
Performance:
-50
tRAC
tCAC
tAA
tRC
tHPC
RAS Access Time
CAS Access Time
Access Time from Address
Cycle Time
EDO Mode Cycle Time
50 ns
13 ns
25 ns
84 ns
20 ns
-60
60 ns
15 ns
30 ns
104 ns
25 ns
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Single +3.3 V
鹵
0.3 V Power Supply
CAS-before-RAS refresh, RAS-only-refresh
Decoupling capacitors mounted on substrate
All inputs, outputs and clocks are fully LV-TTL compatible
Serial presence detects (optional)
Utilizes four 1M
脳
16 -DRAMs in TSOPII-50/44
and two 1M x 4 - DRAMs in SOJ 26/20 packages
1024 refresh cycles / 16 ms with 10 / 10 addressing (Row / Column)
Gold contact pad
Card Size: 133,35mm x 25,40 mm x 5,30 mm
This DRAM product module family is intended to be fully pin and architecture compatible
with the 168pin unbuffered SDRAM DIMM module family
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Semiconductor Group
1
2.97

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