鈥?/div>
Replaces electromechanical relays and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS technology. Providing embedded protective functions.
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
5
7
9
18
17
14
13
4
8
2
6
Symbol Function
V
bb
Positive power supply voltage.
Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 4 and also for low
thermal resistance
IN1
Input 1 .. 4,
activates channel 1 .. 4 in case of
IN2
logic high signal
IN3
IN4
OUT1
Output 1 .. 4,
protected high-side power output
OUT2
of channel 1 .. 4. Design the wiring for the
OUT3
max. short circuit current
OUT4
ST1/2
Diagnostic feedback 1/2
of channel 1 and
channel 2, open drain, low on failure
ST3/4
Diagnostic feedback 3/4
of channel 3 and
channel 4, open drain, low on failure
GND1/2
Ground 1/2
of chip 1 (channel 1 and channel 2)
GND3/4
Ground 3/4
of chip 2 (channel 3 and channel 4)
Pin configuration
(top view)
V
bb
GND1/2
IN1
ST1/2
IN2
GND3/4
IN3
ST3/4
IN4
V
bb
1
2
3
4
5
6
7
8
9
10
鈥?/div>
20
19
18
17
16
15
14
13
12
11
V
bb
V
bb
OUT1
OUT2
V
bb
V
bb
OUT3
OUT4
V
bb
V
bb
1
)
With external current limit (e.g. resistor R
GND
=150
鈩?
in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Semiconductor Group
1 of 15
2003-Oct-01
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