PSN2450A
9939 Via Pasar 鈥?San Diego, CA 92126
TEL (858) 621-2700 FAX (858) 621-2722
PHASE LOCKED LOOP
Rev A1
PHASE NOISE (1 Hz BW, typical)
0
-40
-80
FEATURES
鈥?Frequency Range: 2463 - 2465 MHz
鈥?Step Size:
1000 KHz
鈥?PLL - Style Package
APPLICATIONS
鈥?Telecommunications
鈥?Satellite
鈥?Telemetry
PERFORMANCE SPECIFICATIONS
Frequency Range
-120
-160
-200
100 Hz
1 kHz
VALUE
2463
-
2465
-100
-25
-70
4.5鹵1.5
50
1000
250
5
5
-40 to 85
PLL
5
30
Vdc
mA
10 kHz
UNITS
MHz
dBc/Hz
dBc
dBc
dBm
100 kHz
Phase Noise @ 10 kHz offset (1 Hz BW, typ.)
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
Power Output
Load Impedance
Step Size
Charge Pump Output Current
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
Package Style
鈩?/div>
KHz
碌螒
mSec
mSec
擄C
POWER SUPPLY REQUIREMENTS
Supply Voltage (Vcc, nom.)
Supply Current (Icc, typ.)
All specifications are typical unless otherwise noted and subject to change without notice.
APPLICATION NOTES
鈥?/div>
AN-107
鈥?/div>
AN-200
鈥?/div>
AN-201
: How to Solder Z-COMM VCOs / PLLs
: Mounting and Grounding of Z-COMM PLLs
: PLL Fundamentals
AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz<
f
o s c
<40 MHz
Frequency Synthesizer: National Semiconductor - LMX2326
漏 Z-Communications, Inc.
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