鈻?/div>
FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
DUAL BANK FLASH MEMORIES
鈥?UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8)
鈥?UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors)
鈥?Concurrent operation: READ from one
memory while erasing and writing the
other
UP TO 256 Kbit BATTERY-BACKED SRAM
27 RECONFIGURABLE I/O PORTS
ENHANCED JTAG SERIAL PORT
PLD WITH MACROCELLS
鈥?Over 3000 Gates of PLD: CPLD and
DPLD
鈥?CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
鈥?DPLD - user defined internal chip select
decoding
27 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
The can be used for the following functions:
鈥?MCU I/Os
鈥?PLD I/Os
鈥?Latched MCU address output
鈥?Special function I/Os.
鈥?16 of the I/O ports may be configured as
open-drain outputs.
IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
鈥?Built-in JTAG compliant serial port allows
full-chip In-System Programmability
鈥?Efficient manufacturing allow easy
product testing and programming
鈥?Use low cost FlashLINK cable with PC
PAGE REGISTER
鈥?Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
PROGRAMMABLE POWER MANAGEMENT
Figure 1. Packages
PQFP52 (M)
PLCC52 (J)
TQFP64 (U)
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HIGH ENDURANCE:
鈥?100,000 Erase/WRITE Cycles of Flash
Memory
鈥?1,000 Erase/WRITE Cycles of PLD
鈥?15 Year Data Retention
5V鹵10% SINGLE SUPPLY VOLTAGE
STANDBY CURRENT AS LOW AS 50碌A(chǔ)
June 2004
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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