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PSD4235G2 Datasheet

  • PSD4235G2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MC...

  • 89頁

  • ETC

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PSD4235G2
Flash In-System Programmable (ISP) Peripherals
For 16-bit MCUs (5V Supply)
PRELIMINARY DATA
FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU
based applications that includes configurable
memories, PLD logic and I/O:
s
Dual Bank Flash Memories
鈥?4 Mbit of Primary Flash Memory (8 uniform
sectors, 32K x 16)
鈥?256 Kbit Secondary Flash Memory with 4
sectors
鈥?Concurrent operation: read from one memory
while erasing and writing the other
s
s
s
s
Programmable power management
High Endurance:
鈥?100,000 Erase/Write Cycles of Flash Memory
鈥?1,000 EraseWrite Cycles of PLD
鈥?15 Year Data Retention
s
Single Supply Voltage
鈥?5V 鹵10%
Memory Speed
鈥?70ns Flash memory and SRAM access time
s
64 Kbit SRAM (Battery Backed)
PLD with macrocells
鈥?Over 3000 Gates of PLD: CPLD and DPLD
鈥?CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs)
鈥?DPLD 鈥?user defined internal chip select de-
coding
Figure 1. Packages
s
Seven l/O Ports with 52 I/O pins
鈥?52 individually configurable I/O port pins that
can be used for the following functions:
鈥?MCU I/Os
鈥?PLD I/Os
鈥?Latched MCU address output
鈥?Special function l/Os
鈥?l/O ports may be configured as open-drain
outputs
TQFP80 (U)
s
In-System Programming (ISP) with JTAG
鈥?Built-in JTAG compliant serial port allows full-
chip In-System Programmability
鈥?Efficient manufacturing allow easy product
testing and programming
鈥?Use low cost FlashLINK cable with PC
s
Page Register
鈥?Internal page register that can be used to ex-
pand the microcontroller address space by a
factor of 256
December 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/89

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