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PPC401GF-MC50C2 Datasheet

  • PPC401GF-MC50C2

  • 32-Bit Microprocessor

  • 329.96KB

  • 36頁

  • ETC

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PowerPC 401GF
32-Bit RISC
Embedded Controller
Features
鈥?PowerPC
鈩?/div>
RISC CPU core and instruction
set architecture
鈥?Pipelined CPU core runs at up to 4X the
external bus clock rate
鈥?Separate instruction cache and write-back/
write-through data cache, both two-way set-
associative
鈥?Multiplexed external bus
鈥?Configurable interfaces to memory and
peripherals:
鈥揇evice-paced wait states
鈥?-,16-, or 32-bit bus widths
鈥揚(yáng)rogrammable hold states
鈥?Flexible interface to external bus masters
鈥?Integrated power management and clock gen-
erator
鈥?Big-Endian or Little-Endian device attachment
鈥?Hardware support for unaligned accesses
鈥?Thirty-two 32-bit general purpose registers
Data
Sheet
Overview
The 401GF RISC controller consists of a
pipelined CPU core, data cache unit (DCU),
instruction cache unit (ICU), memory
management unit (MMU), bus control unit (BCU),
asynchronous interrupt controller, and JTAG
debug port.
The internal 2KB instruction cache and 1KB data
cache reduce overhead for data transfers to or
from external memory. Each cache unit consists
of a data array and a tag array, and the MMU is
provided for cache management and addressing.
The CPU core consists of general purpose regis-
ters (GPR), special purpose registers (SPR),
ALU, barrel shifter, and the control logic required
to manage data flow and instruction execution
within the CPU core.
Applications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Set-top boxes
Consumer electronics and video games
Telecommunications and networking
Office automation (printers, copiers, fax)
Personal digital assistants (PDA)
JTAG
Port
Interrupt
Controller
Power
Mgmt
Timers: PIT, FIT, 64-bit base
RISC CPU Core
1X-4X Core Clocking
Thirty-two 32-bit GPRs
Real-Mode MMU
Data
Cache Unit
Instruction
Cache Unit
Specifications
鈥?CPU core frequency to 50 MHz, I/Os to
25 MHz
鈥?Interfaces to both 3V and 5V technologies
鈥?Low-power 3.3V operation with doze/nap/
sleep modes
鈥?Low-cost 80-lead TQFP package
鈥?0.5
碌
m triple-level-metal CMOS
Clock
Gen
Bus Control Unit
OSC MemClk
Address/
Data Bus
Bus
Controls
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