碌TrenchMOS鈩?/div>
ultra low level FET
Rev. 02 鈥?23 February 2004
Product data
1. Product pro鏗乴e
1.1 Description
Dual common drain N-channel enhancement mode 鏗乪ld-effect transistor in a plastic
package using TrenchMOS鈩?technology.
1.2 Features
s
Surface mounted package
s
Very low threshold
s
Low pro鏗乴e
s
Fast switching.
1.3 Applications
s
Portable appliances
s
Battery management
s
PCMCIA cards
s
Load switching.
1.4 Quick reference data
s
V
DS
鈮?/div>
30 V
s
P
tot
鈮?/div>
2.3 W
s
I
D
鈮?/div>
7.8 A
s
R
DSon
鈮?/div>
21.5 m鈩?
2. Pinning information
Table 1:
Pin
1,8
2,3
4
5
6,7
Pinning - SOT530-1 (TSSOP8), simpli鏗乪d outline and symbol
Description
drain (d)
source1 (s1)
gate1 (g1)
gate2 (g2)
source2 (s2)
g1
1
Top view
4
MBK885
Simpli鏗乪d outline
8
5
Symbol
d
d
s1
g2
s2
mbl600
SOT530-1 (TSSOP8)
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