PM8372
PBC 4x2G
Preview
4-Port FC/GE Retimer and FC-AL Port Bypass Controller
GENERAL
鈥?Supports 4 Fibre Channel Physical
Interfaces at 1.0625 or 2.125 Gbit/s
per Fibre Channel 鈥?Physical Interface
(FC-PI) or 4 Gigabit Ethernet Retimers
at 1.25 Gbit/s per IEEE 802.3z.
鈥?Each port supports FC 1G or 2G rate
detection/auto-selection.
鈥?Supports Arbitrated Loop and Retimer
configuration.
鈥?Each port is independently selectable
to perform retimer, reclocker or
bypass-path function.
鈥?Non-blocking crossconnect supports
protection switching, broadcasting and
multicasting.
鈥?Automatic selection of retimer,
reclocker or bypass-path function to
minimize latency and jitter when a disk
is bypassed.
鈥?Per-port receive monitoring for loss of
signal, error rate, and link level
violations.
鈥?Supports single-ended or differential
106.25 MHz reference clock REFCLK
for Fibre Channel applications or
125 Mhz reference clock for Gigabit
Ethernet applications.
TEST AND CONTROL
鈥?Supports optional 2-pin serial
management interface using selectable
Two-Wire Interface (TWI) or MDC/MDIO
protocol for configuration and diagnostic
access.
鈥?For normal mode of operation, a
management interface is not required.
鈥?Digital Loss of Link (DLOLB) detect
outputs for monitoring individual or
multiple links. DLOLB can be
programmed to indicate excessive
8B/10B code error rate, loss of
synchronization, loss of signal, CRC32
errors, or comma density.
鈥?Interrupt output to flag changes in
bypass state and DLOLB error
conditions.
鈥?Supports built-in self-test (BIST) via
internal Fibre Channel pattern
generation and checking.
鈥?External control pins can be overwritten
by registers.
HIGH-SPEED INTERFACE
鈥?High-speed outputs with selectable pre-
emphasis per port to counteract
dielectric losses and allow maximum
reach on printed circuit boards.
鈥?Selectable receive input equalization for
improved signal integrity.
鈥?Minimized board footprint and improved
signal integrity achieved because:
鈥?/div>
No external components are required
to interface the high-speed signals to
optics, coax, or serial backplanes
using the internal AC coupling
capacitors and terminating resistors.
鈥?/div>
Receive input termination of 100
鈩?/div>
or
150
鈩?/div>
differential is selectable.
鈥?/div>
Source output impedance of 100
鈩?/div>
or
150
鈩?/div>
differential is programmable.
BLOCK DIAGRAM
TDOP[2]
TDON[2]
RDIP[1]
RDIN[1]
10
2
2
10
SERDES/
Reclocker
Tx
Control
Rx
Retimer/
Monitor
Loopback/
Failover
Cross
Connect
Rx
Retimer/
Monitor
Tx
Control
2
10
SERDES/
Reclocker
2
RDIP[2]
RDIN[2]
TDOP[3]
TDON[3]
10
TDOP[1]
TDON[1]
RDIP[0]
RDIN[0]
10
2
2
10
SERDES/
Reclocker
Tx
Control
Rx
Retimer/
Monitor
Rx
Retimer/
Monitor
Tx
Control
2
10
SERDES/
Reclocker
2
RDIP[3]
RDIN[3]
TDOP[0]
TDON[0]
10
TCK
TMS
TDI
TDO
TRSTB
Pattern
Generator/
Comparator
PMC-2021698
Issue 2
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
AND FOR ITS CUSTOMERS鈥?INTERNAL USE
RECEQUALIZ[1:0]
PREEMPH[1:0]
RECRET_SEL
BYPASSB[3:0]
RET_LPBK
RET_MODE
FC_GE_RET_SEL
HALF_RATE
AUTO_RATE_SEL
REFCLK_S
REFCLK_P
JTAG
CDRU
Impedance
Control
Two Wire
Interface
RPRES
REFCLK_N
CLK_SEL
EXTCAP
TX100/
150[3:0]
RX100/
150[3:0]
MDC_SCL
MDIO_SDA
DVPRTAD[4:0]
RESETB
TWISEL
Control Block
DLOLB
PORT_DLOLB[3:0]
INTRB
OENB
TRUST_MODE
MON_BYP_PORT
DLOLBYP_MSK
漏 Copyright PMC-Sierra, Inc. 2003.
All rights reserved.
PM8372相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
Analog IC
ETC
-
英文版
Analog IC
ETC
-
英文版
Analog IC
ETC
-
英文版
TEMUX 336 High Density T1/E1 Framer, VT/TU Mapper & M13 Mux ...
PMC-Sierra, Inc
-
英文版
TEMUX 168 High Density T1/E1 Framer, VT/TU Mapper & M13 Mux ...
PMC-Sierra, Inc
-
英文版
High-Density 32-Channel T1/E1/J1 Framer with Integrated VT/T...
PMC-Sierra, Inc
-
英文版
M13 Multiplexer/Demultiplexer
PMC
-
英文版
M13 Multiplexer/Demultiplexer
PMC [PMC-S...
-
英文版
M13 MULTIPLEXER
PMC [PMC-S...
-
英文版
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M...
PMC
-
英文版
High Density T1/E1 Framer with Integrated VT/TU Mapper and M...
PMC [PMC-S...
-
英文版
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M...
PMC [PMC-S...
-
英文版
High Density 84-Channel T1/E1/J1 Framer with Integrated VT/T...
PMC
-
英文版
High Density 84-Channel T1/E1/J1 Framer with Integrated VT/T...
PMC [PMC-S...
-
英文版
8-Channel 1.0-1.25 Gbps Transceiver
PMC
-
英文版
8-Channel 1.0-1.25 Gbps Transceiver
PMC [PMC-S...
-
英文版
4-Channel 1.0-1.25 Gbps Transceiver
PMC
-
英文版
4-Channel 1.0-1.25 Gbps Transceiver
PMC [PMC-S...
-
英文版
4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-...
PMC
-
英文版
4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-...
PMC [PMC-S...
1
2
