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High speed serial backplanes
Gigabit Ethernet links
FibreChannel links
Intra-system interconnect
ASIC to PMD link
EXAMPLE ARCHITECTURE
The first figure on the next page shows
the OctalPHY in a switch application.
This implementation uses eight channels
of 1.25 Gbaud per linecard, requiring
only 32 signal pins per linecard and 128
for the switch card, providing up to
32 Gbps total payload capacity to the
switch fabric.
The 5-bit DDR interface of the OctalPHY
saves pins on the switch device. An
additional OctalPHY operated in trunking
mode creates a cost effective 10 Gbps
uplink, capable of directly driving copper
or various optical transports.
The dotted lines in the figure depict the
system clock domains. Note that even
though the recovered clock from any or
all serial links may be asynchronous to
the local clock, the OctalPHY bridges
these domains so that the switch fabric
and linecards may be designed in only a
single clock domain.
The OctalPHY creates a highly
integrated and cost effective physical
layer solution for Gigabit Ethernet or
FibreChannel external interfaces.
GENERAL DESCRIPTION
The OctalPHY
TM
is an octal PHYsical
layer transceiver ideal for systems
requiring large numbers of point-to-point
gigabit links. It provides eight individual
serial channels capable of operation at
up to 1.25 Gbps, which may be grouped
together to form a single 12.5 Gbps
bidirectional link.
The OctalPHY includes 8B/10B block
coding logic (compliant with 802.3z
Gigabit Ethernet and FibreChannel
requirements) which produces run length
limited data streams for serial trans-
mission.
A receive FIFO optionally aligns all
incoming parallel data to the local clock
domain, adding or removing IDLE
sequences as required. This simplifies
implementation of the upstream ASIC by
removing the requirement to deal with
multiple clock domains.
When trunking is enabled, the OctalPHY
can remove cable skew differences
equivalent to several meters, presenting
8-byte data vectors at the receive
interface exactly as they were trans-
mitted.
BLOCK DIAGRAM
Transmit Channel A (1 of 8)
Parallel
Data In
FIFO
TX Byte
Clock
PCS
8B/10B
Encoder
10
Serializer
Serial
Transmit
Data
Receive Channel A (1 of 8)
Parallel
Data Out
10
FIFO
PCS
10B/8B
Decoder
Deserialize &
Byte Align
Clock
Recovery
Serial
Receive
Data
RX Byte
Clock
REFCLK
Clock Synthesizer
PLL LOCK
PMC-2000672 (R3)
Common Control Logic
MDC/MDIO
Serial
Management
Static Controls
漏 Copyright PMC-Sierra, Inc. 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
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