PMC-Sierra,Inc.
PM8313
D3MX
鈥?Provides a generic 8-bit
microprocessor interface for
configuration, control, and status
monitoring.
鈥?Low power 5 V CMOS technology.
鈥?Available in a high density (28 by
28 mm) 208-pin Plastic Quad Flat
Pack (PQFP) package.
M13 Multiplexer/Demultiplexer
FEATURES
鈥?Integrates a complete M13 multiplexer/
demultiplexer in a single monolithic
device.
鈥?Integral framer supports the M23 or C-
bit parity DS3 format with path
maintenance datalink processing and
bit-oriented code support for Far-End
Alarm and Control (FEAC) channel
termination.
鈥?Supports either the M12 or the G.747
formats to allow DS1 or E1 signals to
be multiplexed into a DS3 signal.
鈥?Allows the M12 stages to be bypassed
allowing direct input of DS2 signals.
鈥?Generates an interrupt upon detection
of various alarms, events, or changes
in status. Identification of interrupt
sources, masking of interrupt sources,
and acknowledgement of interrupts is
provided via internal registers.
鈥?Application-compatible with the
PM4351 COMET T1 Transceiver,
PM4341A T1XC T1 Transceiver,
PM4344 TQUAD Quad T1 Framer,
PM4388 TOCTL Octal T1 Framer,
PM6341 E1XC E1 Transceiver,
PM6344 EQUAD Quad E1 Framer,
PM6388 EOCTL Octal E1 Framer,
PM4314 QDSX Quad E1/T1 LIU, and
the PM7344 S/UNI
廬
-MPH.
M23 AND M12 MULTIPLEX/
DEMULTIPLEX SECTIONS
鈥?Supports combination of four DS1 bit
streams or the combination of three E1
bit streams per G.747 into a single
M12 stream.
鈥?Supports per-DS2 payload loopback
requests via C-bits or microprocessor
control.
鈥?Accumulates DS2 M-bit, F-bit, and
G.747 framing bit/word error events.
鈥?Supports DS2 AIS assertion based on
DS3 LOF, or under microprocessor
control.
鈥?Supports DS2 tributary AIS activation/
deactivation in either direction under
microprocessor control.
鈥?Inserts/detects per-DS1 payload
loopback requests transmitted via
C-bits.
DS3 FRAMER SECTION
鈥?Detects/inserts DS3 Alarm Indication
Signal (AIS) and Idle signal - operates
correctly in the presence of 10-3 Bit
Error Ratio (BER).
鈥?Extracts/inserts the X,P,M,F,C and the
stuff opportunity bits and serializes for
optional external processing.
鈥?Extracts/inserts the C-bit parity mode
path maintenance datalink and
serializes for optional external
processing.
鈥?Extracts/inserts the C-bit parity bit-
oriented codes in the FEAC channel.
鈥?Detects and accumulates EXcessive
Zeros (EXZ), Loss Of Signal (LOS),
Line Code Violations (LCVs) P-bit,
F-bit, or M-bit errors, C-bit parity errors
and Far-End Block Errors (FEBEs).
鈥?Supports DS3 line loopback and DS3
diagnostic loopback modes to assist in
fault isolation.
APPLICATIONS
鈥?M23 or C-Bit Parity Format DS1 to
DS3 Mux/Demux Equipment
鈥?Fractional T3 Access Equipment
鈥?DS2-to-DS3 Mux/Demux Equipment
鈥?DS1-to-DS3 Mux/Demux Equipment
Supporting G.747 Tributary Format
BLOCK DIAGRAM
TDLSIG/TDLUDR
TDLCLK/TDLINT
TDLEOMI
TOHCLK
TOHEN
TOHFP
TIMFP
TICLK
GD2CLK
TOH
#1
XBOC
Transmit
FEAC
XFDL
Transmit
HDLC
Tx
O/H
Access
MX12
M12
MUX/
DEMUX
MX23
M23
MUX/DEMUX
DS2
FRMR
Framer
RD1CLK4
RD1DAT4
TD1CLK4
TD1DAT4
RD1DAT[3:1]
RD1CLK[3:1]
RD1CLK[3:1]
RD1DAT[3:1]
TCLK
TPOS/TDAT
TNEG/TMFP
B3ZS
Decode
TRAN
DS3 Transmit
Framer
RCLK/VCLK
RPOS/RDAT
RNEG/RLCV
B3ZS
Decode
FRMR
DS3 Receive
Framer
One of seven M12
PMON
Perfor-
mance
Monitor
Counters
#2 - #7
Remaining Six M12
RBOC
Receive
FEAC
RFDL
Receive
HDLC
Rx
O/H
Access
TD1CLK[28:5]
TD1DAT[28:5]
RD1CLK[28:5]
RD1DAT[28:5]
MPIF
Microprocessor
Interface
ROCLK, RODAT,
RMFP, RMSFP,
ROHP, ROHCLK
ROHFP, ROH,
RLOS, REXZ,
RAIS, ROOF/
RRED, RFERF
D[7:0]
A[7:0]
PMC-920522 (R10)
RDLSIG/RDLEOM
RDLCLK/RDLINT
漏 1998 PMC-Sierra, Inc. October, 1998
TD2CLK
A8/TRS
ALE
CSB
WRB
RDB
RSTB
INTB
1
2
