Preliminary
PM7800
PALADIN-10
Digital Correction Signal Processor
FEATURES
鈥?Digitial Adaptive Pre-Distortion for
wideband linearization of power
amplifiers in wireless basestations.
鈥?Digitial Correction for Analog
Quadrature Modulation Distortion.
鈥?Digital Soft Pre-compression for
efficiency management.
鈥?Input Signal Bandwidth up to 10 MHz.
Sample rate up to 80 MHz.
鈥?Programmable, variable input data
rate.
鈥?16-bit microprocessor bus interface for
adaptive control processor
compensation engine.
鈥?Serial interface (configurable to SPI or
I2C operation) for update of power and
carrier values.
鈥?48 general-purpose IO pins, eight of
which are edge-triggered interrupt
sources.
鈥?Standard five-signal IEEE 1149.1
JTAG test port for boundary scan
board test purposes.
APPLICATIONS
鈥?Multi-carrier WCDMA Base
Transceiver Subsystems (BTS).
鈥?CDMA2000 BTS (requires firmware
upgrade).
鈥?GSM/TDMA/EDGE BTS (requires
firmware upgrade).
PACKAGING
鈥?Low-power 1.8 V CMOS core logic
with 3.3 V CMOS/TTL compatible
digital inputs and digital outputs.
鈥?Industrial temperature range (-40 擄C to
+85 擄C).
鈥?304-pin SBGA with a body size of
31mm x 31mm.
BLOCK DIAGRAM
PALADIN-10 Padring
JTAG
DCLK
REFCLK
CPUCLK
PALADIN-10 Core
RESET_N
VREF
SCS_N
SD
SCLK
HOP_N
Input Module
Pre-
Predistorter
Circuitry
Predistortion
Filter
Modulation
Circuitry
VD
PALADIN-10
VOBS
Capture
Module
CPU
Interface
GPIO
Control
ADR
PMC-2001613 (P1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
DAT
漏 Copyright PMC-Sierra, Inc. 2000
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