Preliminary
PM7389
FREEDM 84A1024
Frame Engine and Datalink Manager
FEATURES
鈥?Single-chip multi-channel packet
processor supporting a maximum
aggregate bandwidth of 156 Mbit/s for
line rate throughput transfers of packet
sizes from 40 to 9.6 Kbytes, for up to
an aggregate of 84 T1s, 63 E1s, or 3
DS-3s.
鈥?Provides simultaneous support of
PPP, Frame Relay, Multilink-PPP and
Multilink-Frame Relay protocols.
Alternative protocols supported via
HDLC termination and full packet store
of the data within the HDLC structure.
鈥?Support for 3 egress fragmentation
sizes (128, 256, and 512 bytes)
configurable on a per multilink bundle.
Optionally full packet transfers are
supported on a per bundle basis.
鈥?Supports up to 42 multilink bundles
with up to 12 member links per bundle.
These bundles are composed of
independent HDLC channels.
鈥?Support for up to 100ms of intra bundle
skew in the receive direction when
supporting the minimum fragment size.
鈥?Support for PPP header compression
as per RFC 1661.
鈥?Link Control protocol packets are
identified by the PID as control
protocols and will be forwarded to the
Any-PHY interface.
FRAME RELAY
鈥?Link layer address lookup can be
performed based on HDLC channel
and 10 bit DLCI for HDLC channels
supporting Frame Relay protocols.
鈥?The lookup algorithm can support a
maximum of 16 K connection
identifiers (CIs) amongst multilink FR
bundles. The connection identifiers
are ignored in singlelink FR channels.
鈥?Control frames are identified and
forwarded to Any-PHY interface.
鈥?12 bit sequence numbers supported.
鈥?FECN, BECN, and DE ingress
processing as per FRF.12.
MULTILINK PPP AND FRAME
RELAY BUNDLES
鈥?Capable of supporting fragment sizes
from 1 to 9.6 Kbytes.
PPP
鈥?Support for 16 COS levels in
accordance with RFC 2686.
鈥?Either 12 bit or 24 bit sequence
number, with short and long fragment
header formats, is supported.
BLOCK DIAGRAM
BCLK
AD[31:0]
ADSB
CSB
WR
BURSTB
BLAST
READYB
BTERMB
WRDONEB
INTHIB
INTLOB
BUSPOL
RSTB
PMCTEST
SCAN_EN
DLLTEST
SYSCLK
TCLK[0]
TCLK[4]
TCLK[8]
TD[0]
TD[4]
RD[8]
TDO
TDI
TCK
TMS
TRSTB
DDLL-
140
JTAG
Microprocessor I/F (BUMP2)
Tx ANY-PHY
I/F (TAPI-12)
Egress
Queue
Manager
(EQM-12)
Tx
Fragment
Builder
(TFRAG)
SRAM
Controller
(SRAMC)
ACIFP
CIFPOUT
ADATA[7:0]
ADP
APL
AV5
AJUST_REQ
AACTIVE
ADETECT[1:0]
Insert
SBI
(INSBI)
Transmit
Channel
Assigner
(TCAS-12)
Tx HDLC
Processor /
Partial Packet
Buffer
(THDL-12)
TXCLK
TXADDR[15:0]
TPA
TXDATA[15:0]
TXPRTY
TRDY
TSX
TEOP
TMOD
TERR
CCDAT[35:0]
CCADD[17:0]
CCWEB
CCSELB
CCBSELB[1:0]
CBDAT[47:0]
CBADD[12:0]
CBWEB
CBCSB
CBRASB
CBCASB
CBBS[1:0]
RXCLK
RXADDR[3:0]
RPA
RENB
RXDATA[15:0]
RXPRTY
RVAL
RSX
RSOP
REOP
RMOD
RERR
Performance
Monitor
(PM-12)
REFCLK
Rx HDLC
Processor /
Partial Packet
Buffer
(RHDL-12)
CB DRAM
Controller
(CB_DRAMC)
DDATA[7:0]
DDP
DPL
DV5
DC1FP
Extract
SBI
(EXSBI)
Receive
Channel
Assigner
(RCAS-12)
Rx
Fragment
Builder
(RFRAG)
Frame
Builder
(FRMBLD)
Ingress
Queue
Manager
(EQM-12)
Rx ANY-PHY
I/F
(RAPI-12)
RS DRAM
Controller
(RS_DRAMC)
RSDAT[31:0]
RSADD[12:0]
RSWEB
RSCSB
RSRASB
RSCASB
RSBS[1:0]
DQM
RCLK[0]
RCLK[4]
RCLK[8]
RD[0]
RD[4]
RD[8]
Data
Control
PMC-1991477 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
漏 Copyright PMC-Sierra, Inc. 2001
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