PMC-Sierra,Inc.
PM7375
LASAR-155
鈥?Provides leaky bucket Peak Cell Rate
(PCR) enforcement using eight
programmable peak queues coupled
with sub-rate control on a per-VC
basis.
鈥?Implements Sustainable Cell Rate
(SCR) enforcement using a token
generation mechanism on a per-VC
basis.
鈥?Provides an internal VC parameter
storage for both the 128 transmit and
128 receive VCs to simplify the design
of the ATM adapter and to sustain a
high data throughput rate.
ATM SAR and PHY Processor for PCI Bus
FEATURES
鈥?Combines PHY, ATM, AAL5, and PCI
DMA Controller on a single device to
simplify the design, programming, and
manufacturing of ATM adapters.
鈥?Conforms to ATM Forum User-
Network Interface (UNI) Specification
Version 3.1, Bellcore Standard TA-
NWT-001113, and ITU-T
Recommendations I.432 and I.363.
MICROPROCESSOR
INTERFACE
鈥?In slave mode, provides a generic 8-bit
microprocessor port for the
configuration, control, and monitoring
by an optional microprocessor.
鈥?In master mode, allows for the control
of two external devices without glue
logic.
PACKAGING
鈥?Provides a standard 5-signal P1149.1
JTAG test port for boundary scan
board test purposes.
鈥?Implemented in low power, 0.6 micron,
+5 V CMOS technology with TTL and
Pseudo ECL (PECL) compatible inputs
and outputs.
鈥?Packaged in 208-pin Plastic Quad Flat
Pack (PQFP) package.
HOST INTERFACE
鈥?Provides a 32-bit, 33 MHz Peripheral
Component Interconnect (PCI) Local
Bus Specifications Version 2.1
interface and supports both bus-
master and bus-slave access modes.
Other 32-bit system buses can be
accommodated using external glue
logic.
鈥?Implements an efficient DMA controller
to manage the transfer of packets
between the SAR engine and the host
memory with minimum PCI Host
intervention. There is no need for a
local packet memory.
鈥?The transmit and receive DMA
channels support scatter/gather
capabilities where a packet can be
stored in non-contiguous buffers.
鈥?Provides an 8-cell FIFO in the transmit
direction and a 96-cell FIFO in the
receive direction to allow for up to
270
碌s
of PCI bus latency in the
receive direction.
MULTIPURPOSE PORT
鈥?In bypass mode, provides an 8-bit
SCI-PHY鈩?or UTOPIA-compliant port
to connect to an external physical layer
processor such as PM7345 S/UNI-
PDH鈩?for DS3/E3 UNI.
鈥?In non-bypass mode, supports the
insertion and extraction of Constant Bit
Rate (CBR) cells that carry encoded
video and audio signals.
APPLICATIONS
鈥?ATM Workstations and Adapters
鈥?ATM Bridges, Switches, and Hubs
鈥?Multimedia Terminals
BLOCK DIAGRAM
TFIFOFB/TFIFOEB
TCP/TLDCLK
TGFC/TLD
TXPHYBP
TDAT[7:0]
TWRENB
ROMP
TSOC
XOFF
TFPO
TCLK
PHYSICAL LAYER
鈥?Incorporates the industry standard
PMC PM5346 S/UNI
廬
-LITE to provide
SONET and SDH interfaces at STS-
3c/STM-1 (155.52 Mb/s) and STS-1
(51.84 Mb/s) rates.
鈥?Provides on-chip clock recovery and
clock synthesis units that are compliant
with Bellcore TR-NWT-000253 Issue 2
and ITU-T Recommendation G.958
jitter requirements.
鈥?Performs SONET/SDH framer,
overhead, and cell processing
functions at STS-3c/STM-1 and STS-1
rates.
TRCLK+
TRCLK-
TXC
TXD+
TXD-
Transmit
ATM Traffic
Shaper
Transmit
Line
Interface
Transmit
Framer and
Overhead
Processor
Transmit
ATM Cell
Processor
SAR
Perfor-
mance
Monitor
Transmit
ATM and
Adaptation
Processor
Connection
Parameter
Store
Receive
ATM and
Adaptation
Processor
PCI
DMA
Controller
AD[31:0]
C/BEB[3:0]
PAR
FRAMEB
TRDYB
IRDBY
STOPB
DEVSELB
IDSEL
LOCKB
REQB
GNTB
PERRB
SERRB
PCIINTB
PCICLK
RXD+
RXD-
RRCLK+
RRCLK-
ALOS+
ALOS-
Receive
Line
Interface
Receive
Framer and
Overhead
Processor
Receive
ATM Cell
Processor
Microprocessor
Interface
JTAG Port
PCICLKO
SYSCLK
D[15:0]
A[8:0]
LF+, LF-, LFO
RFIFOEB/
RFIFOFB
RDAT[7:0]
RALM
TDI
RCP/RLDCLK
RGFC/RLD
RSOC
TRSTB
WRB
RDB
INTB
RRDENB
鈥?Supports the simultaneous
segmentation and reassembly of 128
open Virtual Circuits (VCs) in both
transmit and receive directions.
PMC-931138 (R6)
RXPHYBP
漏 1998 PMC-Sierra, Inc. October, 1998
MPENB
RSTB
RCLK
TDO
RFP
TMS
CSB
TCK
ALE
ATM AND ADAPTATION
LAYERS
1
2
