PMC-Sierra,Inc.
PM7364
FREEDM-32
鈥?Supports a mix of channelized and
unchannelized links.
鈥?The maximum aggregate clock rate is
64 MHz. When the device is interfaced
to two T3 or HSSI links, the maximum
aggregate clock rate is 104 MHz.
鈥?For channelized operation, the channel
assignment supports up to 24 timeslots
for a T1 link and 31 timeslots for an E1
link. Timeslots assigned to a common
HDLC channel can be noncontiguous.
鈥?Performs flag delineation, bit de-
stuffing, CRC verification using either
CRC-32 or CRC-CCITT algorithm, and
length checking on receive HDLC
channels.
鈥?Performs flag insertion, bit stuffing, and
FCS calculation using either CRC-32
or CRC-CCITT algorithm and length
checking on transmit HDLC channels.
鈥?On the system side, provides a
33 MHz, 32-bit PCI 2.1-compliant bus
interface.
鈥?Implements efficient transmit and
receive DMA controllers to support
burst data transfers between partial
packet FIFO and packet memory.
鈥?Supports scatter-gather capabilities
whereby a packet can span multiple
buffers.
鈥?Supports line-side loopback on a per-
link basis and system-side loopback on
a per-HDLC channel basis.
鈥?Pin-compatible and software-
compatible with the PM7366
FREEDM-8鈩?
鈥?Provides a standard 5-signal P1149.1
JTAG test port for boundary scan test
board purposes.
鈥?Implemented in low power 3.3 V
CMOS technology with 5 V-tolerant
inputs.
鈥?Packaged in a 256-pin Ball Grid Array
(BGA) package.
Frame Engine and Datalink Manager
FEATURES
鈥?High density HDLC controller ideal for
Internet access, Frame Relay, and
DSLAM equipment supporting rates
ranging from 56 Kbit/s to 52 Mbit/s.
鈥?Supports 32 full-duplex and
independently-timed links.
鈥?Supports 128 full-duplex HDLC or
transparent channels.
鈥?Supports a TimePipe鈩?architecture
that enables any physical link to be
flexibly mapped to one or more HDLC
channels.
鈥?Provides 8 KB partial packet FIFO in
each transmit and receive direction to
compensate for PCI bus latency during
data transfers. The 8 KB partial packet
FIFO is arranged as 512 blocks of 16-
byte buffers.
鈥?The TimePipe architecture supports
programmable assignment of partial
packet buffers to HDLC channels.
鈥?Two physical links can support up to
52 Mbit/s; the remaining six physical
links can individually support up to
10 Mbit/s.
APPLICATIONS
鈥?Ideal for applications requiring HDLC,
PPP, and transparent protocol
processing for physical links, such as
T1, E1, T3, E3, xDSL, and HSSI
鈥?Frame-based Interfaces for Internet
Access and DSLAM equipment
鈥?FUNI or Frame Relay service
interworking interfaces for ATM
switches and multiplexers
BLOCK DIAGRAM
RBCLK
RBD
AD[31:0]
C/BEB[3:0]
PAR
FRAMEB
RD[31:0]
RCAS
Receive
Channel Assigner
RHDL
Receive HDLC
Processor/
Partial Packet Buffer
PMON
Performance Monitor
TD[31:0]
THDL
Transmit HDLC
Processor/
Partial Packet Buffer
TimePipe
鈩?/div>
Architecture
JTAG Port
RMAC
Receive
DMA
Controller
GPIC
PCI
Controller
TMAC
Transmit
DMA
Controller
TRDYB
IRDYB
STOPB
DEVSELB
IDSEL
LOCKB
REQB
GNTB
PERRB
SERRB
PCIINTB
PCICLK
PCICLKO
SYSCLK
RCLK[31:0]
TCLK[31:0]
TCAS
Transmit
Channel Assigner
TBCLK
TRSTB
TDI
TDO
TBD
TMB
TCK
PMCTEST
漏
脙
1998 PMC-Sierra, Inc. October, 1998
PMC-960952 (R4)
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