Preliminary
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY
FEATURES
IMA
鈥?Supports up to 32 T1, E1, G.SHDSL or
unchannelized links and up to 32 IMA
groups with 1 to 32 links/group.
鈥?Link and Group State Machines
implemented on-chip requiring no real
time software in the data path.
鈥?Fully compliant with the ATM Forum
Inverse Multiplexer for ATM (IMA)
1.1 specification and backward
compatible to IMA 1.0.
鈥?Supports both independent transmit
clock (ITC) and common transmit clock
(CTC) modes.
鈥?Supports all IMA Group Symmetry
modes: Symmetric/Asymmetric
configuration and operation.
鈥?Differential delay tolerance of 279 ms
(for T1 links) and 226 ms (for E1 links).
鈥?Performs IMA differential delay
calculation and synchronization.
鈥?Provides programmable limit on
allowable differential delay and
minimum number of links per group.
鈥?Performs ICP and stuff-cell insertion
and removal.
鈥?Supports IMA frame length (M) equal
to 32, 64, 128, or 256.
鈥?Provides IMA layer statistic counts and
alarms for support of IMA Performance
and Failure Alarm Monitoring and MIB
support.
鈥?Provides per link counters for statistics
and performance monitoring.
PM7342
S/UNI廬-IMA-32
LINE INTERFACE
鈥?32 T1, E1, G.SHDSL or unchannelized
links via 2-pin line interfaces.
鈥?Supports a 19.44 MHz Scalable Band-
width Interconnect (SBI) bus interface for
seamless interconnect to the PM8315
TEMUX and PM8316 TEMUX-84.
鈥?SBI supports two Synchronous
Payload Envelopes (SPE). Each SPE
can carry up to 16 T1s or 16 E1s.
UNI
鈥?Each link is software configurable as
either a UNI or part of an IMA group.
鈥?Performs receive cell Header Error
Check (HEC) checking and transmit
cell HEC generation.
鈥?Optionally supports receive cell
payload unscrambling and transmit cell
payload scrambling.
鈥?Provides TC layer statistics counts and
alarms for MIB support.
UTOPIA / ANY-PHY INTERFACE
鈥?Supports 8- and 16-bit UTOPIA L2 and
Any-PHY cell interfaces at clock rates
up to 52 MHz.
鈥?Any-PHY transmit slave appears as a
32 port multi-PHY. The PHY-ID of
each cell is identified using in-band
addressing.
鈥?Any-PHY receive slave appears as a
single device. The PHY-ID of each cell
is identified using in-band addressing.
鈥?UTOPIA L2 transmit and receive slave
appears as a 31-port multi-PHY.
鈥?UTOPIA L2 receive slave can also
appear as a single port with the logical
port provided as a prepend.
TCK
TMS
TDI
TRSTB
TDO
ATM OVER FRACTIONAL T1/E1
鈥?Supports ATM over Fractional T1/E1
compliant with the ATM Forum
AF-PHY-0130.00 specification.
REFCLK
SYSCLK
SBI Add Bus I/F
AC1FP
ADATA[7:0]
ADP
APL
AV5
AJUST_REQ
AACTIVE
ADETECT
32 Clk/Data
RSTB
OE
D[15:0]
A[10:1]
ALE
WRB
RDB
CSB
INTB
BLOCK DIAGRAM
DLL
INSBI
Null
Framer
(SDFR32)
32-chan
x 7 cell
FIFO
(MCFD)
MicroProcess I/F
JTAG
Tx Slave
ATM I/F
TC Layer
(TTTC32)
TCAS
Tx IMA Processor
(TIMA)
32-chan
x
3 cell
FIFO
Any-PHY/
UTOPIA
Tx Slave
(TXAPS)
TSCLK[31:0]
TSDATA[31:0]
CTSCLK
TCLK
TPA
TENB
TADR[10:0]
TCSB
TSOP
TSX
TDAT[15:0]
TPRTY
IDCC
Internal Bus
IDCC
32 Clk/Data
Rx IMA
Protocol
Processor
(RIPP)
Rx Slave
ATM I/F
RSCLK[31:0]
RSDATA[31:0]
SBI Drop Bus I/F
RCAS
TC Layer
(RTTC32)
De-
Framer
(SDDF32)
DC1FP
DDATA[7:0]
DDP
DPL
DV5
32-chan
x 2 cell
FIFO
Rx IMA
Data Processor
(RDAT)
Cell Writer
Cell Reader
31
chan
4 cell
FIFO
Any-PHY/
UTOPIA
Rx Slave
(RXAPS)
EXSBI
RCLK
RPA
RENB
RADR[4:0]
RCSB
RSOP
RSX
RDAT[15:0]
RPRTY
Memory Interface
(MEMI)
PMC-2001523 (p5)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
CBCSB
CBRASB
CBCASB
CBWEB
CBA[11:0]
CBBS[1:0]
CBDQM
CBDQ[15:0]
漏 Copyright PMC-Sierra, Inc. 2002
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