scheduling.
鈥?/div>
Error indication in AAL5 EOM trailer
(set by SAR or classifier) can invoke
errored packet discard, thereby
eliminating need for packet buffers
in external devices.
鈥?Traffic queuing algorithm is highly
configurable on a per connection, per
class, and per port basis.
鈥?Configurable scheduling of 4 classes
of service on every port, with rate
shaping available for the 4 WAN ports.
Configurable traffic parameters
enabling a mix of CBR, VBR, GFR,
and UBR classes.
鈥?Configurable OAM cell queuing and
special handling on all ports.
鈥?VPI/VCI header mapping.
鈥?Supports 700 Mb/s ingress traffic and
700 Mb/s egress traffic aggregated
across all ports.
鈥?Low power 3.3/2.5V CMOS.
鈥?Standard 5 pin P1149 JTAG port.
鈥?352 ball SBGA, 35mm x 35mm.
鈥?/div>
Or single port slave.
MICROPROCESSOR INTERFACE
鈥?66 MHz, 32 bit address/data bus
capable of single or burst access to
internal registers and cell buffers.
鈥?Supports cell/packet transfer to/from
any port, with CRC32 and CRC10
calculation supported in hardware.
鈥?Works seamlessly with
S/UNI-VORTEX and S/UNI-DUPLEX
to implement a system-wide
embedded communication channel.
CONGESTION CONTROL
鈥?Traffic discard thresholds configurable
per connection (independent CLP0
and CLP1 thresholds), per class, per
port, and per direction.
鈥?Guaranteed Frame Rate (GFR)
implemented via CLP0 minimum buffer
size reservation per connection.
BUS INTERFACES
鈥?8/16 bit, 52 MHz UTOPIA L2 bus.
鈥?Line side:
鈥?/div>
Enhanced UTOPIA Tx master
supports 2048 ports. Rx master
supports 32 ports.
鈥?/div>
Or single port slave.
鈥?WAN side:
鈥?/div>
Master (with optional cell length
expansion) supports 4 Tx or Rx
ports.
QUEUING & SCHEDULING
鈥?64k traffic staging queues (one per
connection) individually assignable to
any CoS on any port.
鈥?8k + 20 scheduling queues: 4 CoS
queues per port, 2048 line ports, 4
WAN ports, and 1 processor port.
Ctrl Lines
AD[31:0]
Processor
Interface
SSRAM Interface
LRCLK
LRPA
LRSX
LRSOP
LRDAT[15:0]
LRPRTY
LRENB
LRADR[5:0]
CMAB[18:17]
CMD[33:0]
BLOCK DIAGRAM
CMA[19:0]
CMP[1:0]
CMRWB
CMCEB
Loop Rx
Any-PHY
Que Management &
Scheduling
Loop Tx
Any-PHY
LTCLK
LTPA
LTSX
LTSOP
LTDAT[15:0]
LTPRTY
LTENB
LTADR[11:0]
WRCLK
WRPA
WRSX
WRSOP
WRDAT[15:0]
WRPRTY
WRENB
WRADR[2:0]
WAN Rx
Any-PHY
SDRAM Interface
JTAG Test
Access Port
WAN Tx
Any-PHY
WTCLK
WTPA
WTSX
WTSOP
WTDAT[15:0]
WTPRTY
WTENB
WTADR[2:0]
TMS
TCK
CBDQM[1:0]
SYSCLK
CBCSB
CBRASB
CBCASB
PMC-990146 (P2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
CBDQ[31:0]
CBA[11:0]
CBBS[1:0]
CBRWEB
TRSTB
RSTB
TDO
TDI
OE
漏 1999 PMC-Sierra, Inc.
1
2
