PMC-Sierra,Inc.
PM7324
S/UNI-ATLAS
compliant, per-VC programmable dual
leaky bucket policing with a
programmable action (tag, discard, or
count only) for each bucket, each with
3 programmable 16 bit non-compliant
cell counts.
鈥?Per-PHY single leaky bucket policing
with a programmable action (tag,
discard, or count only)
鈥?Guaranteed Frame Rate (GFR)
Policing with Minimum Cell Rate
Frame Tagging.
鈥?Per-PHY counts include CLP0 cells,
CLP1 cells, OAM cells, errored OAM
cells, unassigned/invalid cells and
policing violations.
鈥?Per-device counts include total cells
received/transmitted, and physical
layer cells.
SATURN User Network Interface ATM Layer Solution
FEATURES
鈥?Monolithic single chip device which
handles bi-directional ATM Layer
functions including VPI/VCI address
translation, cell appending, policing
(ingress only), cell counting and OAM
requirements for 65536 VCs (virtual
connections).
鈥?Instantaneous bi-directional transfer
rate of 800 Mbit/s supports a bi-
directional cell transfer rate of
1.42x106 cells/s.
鈥?Ingress input interface supports an 8 or
16 bit PHY interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
鈥?Ingress output interface supports an 8
or 16 bit SCI-PHY (52 - 64 byte cell)
interface (Utopia Level 1) to a switch
fabric.
鈥?Egress input and output interfaces
support an 8 or 16 bit SCI-PHY (52 -
64 byte cell) interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
鈥?Compatible with a wide range of
switching fabrics and traffic
management architectures.
鈥?Ingress functionality includes a highly
flexible search engine that covers the
entire PHYID/VPI/VCI address range,
dual leaky bucket policing, per-VC cell
counts, OAM-FM and OAM-PM
processing.
鈥?Egress functionality includes direct
address lookup, per-VC cell counts,
OAM-FM and OAM-PM processing.
Per-PHY output buffering scheme
resolves the head-of-line blocking
issue.
鈥?Includes a FIFO buffered 16-bit
microprocessor bus interface for cell
insertion and extraction, deterministic
VC Table access, status monitoring
and configuration of the device.
鈥?Supports DMA access for cell
extraction.
鈥?The UTOPIA and external SRAM
interfaces are 52 MHz max.
PACKAGING
鈥?Provides a standard 5 signal P1149.1
JTAG test port for boundary scan
board test purposes.
鈥?Implemented in low power, 0.35
micron, 3.3 Volt CMOS technology
with 5 Volt tolerant and microprocessor
interface, 3.3V UTOPIA and external
synchronous SRAM interfaces.
鈥?Packaged in 432 pin ball grid array
(BGA) package.
OAM
鈥?ITU-I.610 compliant OAM on both
Ingress and Egress directions.
鈥?Complete Fault Management (AIS,
RDI, CC) processing, for VP/VC,
Segment/End-to-end flows on all VC鈥檚.
鈥?Complete Performance Monitoring
processing, for VP/VC, Segment/End-
to-end, Forward/Backward flows, on
256 Bi-directional VC鈥檚.
APPLICATIONS
鈥?WAN ATM Core and Edge Switches
鈥?ATM Enterprise and Workgroup
Switches
鈥?Access Switches/Multiplexers
CELL COUNTING
鈥?Per-VC counts include CLP0 cells,
CLP1 cells, policing violations.
BLOCK DIAGRAM
To External Synchronous SRAM
ISD[63:0]
ISP[7:0]
ISA[19:0]
ISRWB
ISOEB
ISADSB
ISYSCLK
SCI-PHY
Level1
Interface
(Slave)
Ingress
Output
Cell
Interface
ODAT[15:0]
OPRTY
OSOC
OFCLK
OCA
ORDENB
OTSEN
IDAT[15:0]
IPRTY
IFCLK
ISOC
ICA[1]
IWRENB[1]
IAVALID/ICA[4]
IADDR[4:3]/ICA[3:2]
IADDR[2:0]/IWRENB[4:2]
IPOLL
SCI-PHY Level1/
Level2 Interface
(Slave)
ESD[31:0]
ESP[3:0]
ESA[19:0]
ESADSB
ESRWB
ESOEB
ESYSCLK
SCI-PHY Level1/
Level2 Interface
(Master)
RDAT[15:0]
RPRTY
RRDENB[1]
RCA[1]
RADDR[4:3]/RCA[3:2]
RAVALID/RCA[4]
ADDR[2:0]/RRDENB[4:2]
RSOC
RFCLK
RPOLL
TDAT[15:0]
TPRTY
TWRENB[1]
TCA[1]
TADDR[4:3]/TCA[3:2]
TAVALID/TCA[4]
TADDR[2:0]/TWRENB[4:2]
TSOC
TFCLK
TPOLL
SCI-PHY Level1/
Level2 Interface
(Master)
Ingress
Search
Engine
Ingress
Input
Cell
Interface
Ingress
Cell
Processor
Ingress
Backward
Cell
Interface
PHY
Statistics
Collection
Egress
Backward
Cell
Interface
Egress
Output
Cell
Interface
Egress
Cell
Processor
Egress
Input
Cell
Interface
Ingress
Microprocessor
Cell Interface
Egress
Microprocessor
Cell Interface
JTAG
Interface
Microprocessor Interface
POLICING
鈥?ITU-I.371, ATM Forum TM4.0
To External Synchronous SRAM
PMC-980489 (R2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT鈥橲 CUSTOMERS鈥?INTERNAL USE
漏 1999 PMC-Sierra, Inc.
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