Preliminary
PM73124
AAL1gator鈩?4
4 Link CES/DBCES AAL1 SAR
FEATURES
鈥?Supports four structured/unstructured
T1 or E1 links, or one unstructured
DS3, E3 or STS-1/STM-0 link over an
AAL1 CBR ATM network.
鈥?Compliant with ATM Forum's CES (AF-
VTOA-0078), and ITU-T I.363.1.
鈥?Supports up to 128 VCs.
鈥?Supports n x 64 (consecutive
channels) and m x 64 (non-
consecutive channels) structured data
format with channel associated
signaling (CAS) support.
鈥?Internal E1/T1 clock synthesizers
provided for each line which can be
controlled via internal synchronous
residual time stamp (SRTS) or an
internal programmable weighted
moving average adaptive clocking
algorithm in unstructured mode. Clock
synthesizers can also be controlled
externally to provide customization of
SRTS or adaptive clocking methods.
鈥?Provides transparent transmission of
CCS and CAS and termination of CAS
signaling.
鈥?Compliant with ATM Forum's Dynamic
Bandwidth Circuit Emulation Service
(DBCES) AF-VTOA-0085. Supports
idle channel detection via processor
intervention, CAS signaling, or data
pattern detection. Provides idle
channel indication on a per channel
basis.
鈥?Supports AAL0 mode, selectable on a
per VC basis.
鈥?Provides transmit and receive buffers
which can be used for OAM cells as
well as any other user-generated cells
such as AAL5 cells for ATM signaling.
鈥?Provides an optional 8/16-bit Any-
PHY鈩?slave interface.
鈥?Provides a three cell FIFO for UTOPIA
loopback support on a per VC basis or
a global basis.
TRANSMIT SECTION
鈥?Provides individually enabled per-VC
data and signaling conditioning in the
transmit cell direction and per DS0
data and signaling conditioning in the
transmit line direction.
鈥?Provides per-VC configuration of time
slots allocated, CAS support, partial
cell size, data and signaling
conditioning, ATM Cell header
definition.
鈥?Generates AAL1 sequence numbers,
pointers and SRTS values in
accordance with ITU-T I.363.1.
Multicast connections are supported.
鈥?Provides a patented frame based
calendar queue service algorithm with
anti-clumping add-queue mechanism
that produces minimal CDV. In
unstructured mode uses non-frame
based scheduling to optimize CDV.
LINE INTERFACE
鈥?Supports the following flexible line
interfaces:
鈥?/div>
Four individual T1 or E1 lines.
鈥?/div>
One H-MVIP line at 8 MHz.
鈥?/div>
One unstructured DS3, E3 or STS-
1/STM-0 line.
鈥?Provides lineside loopback support on
a per channel basis.
UTOPIA INTERFACE
鈥?Supports 52 MHz, 8/16-bit Level 2,
Multi-Phy Mode (MPHY) with parity, 8/
16-bit Level 1, SPHY and 8-bit Level 1,
ATM Master modes.
RL_CLK[3:0]
TL_CLK_OE
TL_CLK[3:0]
CRL_CLK
BLOCK DIAGRAM
SYSCLK
RSTB
SCAN_ENB
SCAN_MODEB
TATM_DATA[15:0]
TATM_PAR
TATM_ENB
TATM_SOC
TATM_CLAV
TATM_CLK
RPHY_ADD[4:0]
RATM_DATA[15:0]
RATM_PAR
RATM_ENB
NCLK
CTL_CLK
Clock
MUX
Line Interface
LINE_MODE
4
F0B
H-MVIP
UTOPIA
Interface
4
4
TL_DATA[3:0]
TL_SYNC[3:0]
TL_SIG[3:0]
RL_DATA[3:0]
RL_SYNC[3:0]
A1SP
4
4
RATM_SOC
RATM_CLAV
RATM_CLK
TPHY_ADD[4:0]
Direct
Mode
4
RL_SIG[3:0]
JTAG
RAM
Interface
Processor Interface
External Clock
Interface
RAM_ADSCB
D[15:0]
A[19:0]
TRST
GC_DOUT[3:0]
CGC_VALID
RAM_PAR[1:0]
RAM_WEB[1:0]
CGC_LINE[3:0]
CGC_SER_D
TMS
ACKB
ADAP_STB
WRB
RAM_D[15:0]
RAM_A[16:0]
SRTS_STB
RDB
TCK
RAM_CSB
TDO
CSB
TDI
ALE
RAM_OEB
INTB
PMC-1991273 (P2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
錚?/div>
Copyright PMC-Sierra, Inc. 2001
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