鈥?/div>
Order Path overhead.
Provides UTOPIA Level 3 32-bit wide
System Interface (clocked up to
104 MHz) with parity support for ATM
applications.
Provides SATURN
廬
POS-PHY
Level 3鈩?32-bit System Interface
(clocked up to 104 MHz) for Packet
over SONET (POS), or ATM
applications.
Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from
the line side transmit stream to the line
side receive stream interface.
Provides support for automatic
protection switching including a bi-
directional 4-bit PECL 622 MHz port
for external APS with mate device.
Built-in APS cross-connect for internal
and external 1+1 and 1:n protection
switching.
Provides a standard five signal IEEE
1149.1 JTAG test port for boundary
scan board test purposes.
鈥?Provides a generic 16-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
鈥?Low power 2.5 V CMOS core logic with
3.3 V CMOS/TTL compatible digital
inputs and digital outputs. PECL inputs
and outputs are 3.3 V compatible.
鈥?Industrial temperature range (-40 擄C to
+85 擄C).
鈥?520 pin SBGA package.
鈥?Pin and software compatible with the
PM5358 S/UNI-4x622.
APPLICATIONS
鈥?ATM and Multiservice Switches,
Routers, and Switch/Routers.
鈥?SONET/SDH Add/Drop Multiplexers
with data processing capabilities
鈥?Uplink Cards.
鈥?SONET/SDH ATM/POS Test
Equipment.
鈥?SONET/SDH Transport Equipment.
BLOCK DIAGRAM
Section/
Line DCC
Insertion
Tx
Section O/H
Processor
Section Line Interface
Tx
Line O/H
Processor
TCLK
TFPO
TFPI
Path Crossbar/
APS Cross Connect
Tx
ATM Cell
Processor
Section
Trace Buffer
WAN
Sync.
Section
Trace Buffer
Tx
POS Frame
Processor
Rx
Section O/H
Processor
Section/
Line DCC
Extraction
Rx
Line O/H
Processor
Sync
Status,
BERM
Rx
Path O/H
Processor
Tx
ATM Cell
Processor
JTAG
Test Access
Port
External
APS
Interface
Microprocessor
Interface
RALARM[15:0]
RFPO
RCLK
RDCLK[15:0]
RDCC[15:0]
APREF0,APREF1
APECLV
APSI[3:0]+/-
APSO[3:0]+/-
PMC-2001825 (A1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE
POS_ATMB
TDO
TDI
TMS
TCK
TRSTB
D [7:0]
A [13:0]
ALE
CSB
WRB
RDB
RSTB
INTB
UTOPIA Level 3/
POS-PHY Level 3 System Interface
TXD[15:0]+/-
RXD[15:0]+/-
SD[15:0]
REFCLK+/-
TDREF1, TDREF0
ATP[1:0]
QAVD
QAVS
AVD[8:0]
AVS[8:0]
SPECLV
SDTTL
Tx
Path O/H
Processor
Tx
POS Frame
Processor
TFCLK
TENB
TADR[3:0]
TSX
TCA/TPA
STPA
TSOC/TSOP
TPRTY
TDAT[31:0]
TMOD[1:0]
TEOP
TERR
RFCLK
RENB
RADR[3:0]
RSX
RCA/RVAL
RSOC/RSOP
RPRTY
RDAT[31:0]
RMOD[1:0]
REOP
RERR
漏 Copyright PMC-Sierra, Inc. 2000.
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