PMC-Sierra,Inc.
PM5357
S/UNI-622-POS
microprocessor interface for device
control and register access
鈥?Provides standard IEEE 1149.1 JTAG
test port for boundary scan
鈥?Performs byte stuffing and destuffing
鈥?Checks for minimum and maximum
packet lengths
鈥?Checks for packet abort sequence
鈥?Performs X
43
+1 payload scrambling
鈥?Provides a SATURN POS-PHY Level
2 and an 8-bit 100MHz POS-PHY
Level 3 system interface
鈥?Provides synchronous 256 byte
transmit and receive FIFO buffers
622 Mbit/s ATM and Packet Over SONET Physical Layer Device
FEATURES
GENERAL
鈥?ATM and Packet over SONET/SDH
(POS) OC-12c (622 Mbit/s) PHY
鈥?Provides on-chip clock and data
recovery and clock synthesis
鈥?Exceeds Bellcore-GR-253 jitter
requirements
鈥?Inserts and extracts ATM cells or POS
packets into/from SONET SPE
鈥?Filters and captures Automatic
Protection Switch bytes (K1,K2) and
detects APS byte failure
鈥?Detects signal degrade and signal
failure thresholds crossing alarms
鈥?Captures and debounces
synchronization status byte (S1)
鈥?Extracts and Inserts the 16 or 64-byte
section trace (J0) and path trace (J1)
messages
鈥?Extracts and inserts section/line data
communication channels (DCC)
鈥?Provides circuitry to meet holdover,
wander and long term stability
鈥?Provides a generic 8-bit
ATM
鈥?Implements the ATM Forum User
Network Interface Specification
鈥?Performs cell payload scrambling and
descrambling
鈥?Provides a UTOPIA Level 2 and an 8-
bit 100MHz UTOPIA Level 3 compliant
system interface
鈥?Provides synchronous 4 cell transmit
and receive FIFO buffers
PACKAGING
鈥?Implemented in low power 3.3 Volt
CMOS technology
鈥?Packaged in a 304 SBGA
鈥?Industrial temperature range (-40擄C to
+85擄C)
PACKET OVER SONET/SDH
鈥?Supports direct packet mapping into
SONET/SDH such as PPP, HDLC and
Frame Relay
鈥?Implements the PPP over SONET/
SDH specification according to RFC
1619 and 1662 of the IETF
鈥?Performs flag sequence detection and
insertion
鈥?Performs CRC-CCITT and CRC-32
FCS generation and validation
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
WAN and Edge ATM switches
Multiprotocol switches
Layer 3 switches
Routers, Packet switches and Hubs
BLOCK DIAGRAM
POS_ATMB
TSDCLK
TLDCLK
LIFSEL
TRSTB
TFPI
TFPO
TCLK
TDO
TMS
TSD
TCK
SYSSEL
TLD
TXD+/-
TDREF1,TDREF0
ATP[0]
Section/Line
DCC Insert
Tx
Line
I/F
Tx Section
O/H
Processor
Tx Line O/H
Processor
JTAG Test
Access Port
Tx Path O/H
Processor
TDI
Tx POS
Frame
Processor
Tx ATM Cell
Processor
Utopia ATM Level 2/3
POS-PHY ATM Level 2/3
System Interface
PTCLK
POUT[7:0]
FPOUT
RBYP
PECLV
REFCLK+/-
RXD+/-
RRCLK+/-
SD
C1,C0
ATP[1]
PICLK
PIN[7:0]
FPIN
OOF
Section
Trace Buffer
Path Trace
Buffer
WAN
Synch.
Rx ATM Cell
Processor
Rx POS
Frame
Processor
Microprocessor
Interfaces
Rx
Line
I/F
Rx Section
O/H
Processor
Rx Line O/H
Processor
Rx Path O/H
Processor
Section/Line
DCC Extract
Rx APS, Sync
Status, BERM
TFCLK
TENB
TCA/TPA
TSOC/TSOP
TPRTY
TDAT[15:0]
TMOD
TEOP
TERR
RFCLK
RENB
RCA/RPA
RSOC/RSOP
RPRTY
RDAT[15:0]
RMOD
REOP
RERR
RVAL
RALARM
RFPO
APSP[4:0]
D[7:0]
RSDCLK
RSD
RLDCLK
RLD
A[8:0]
CSB
ALE
RDB
RCLK
RSTB
WRB
INTB
錚?/div>
1999 PMC-Sierra, Inc. January, 1999
PMC-981280 (R2)
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