PMC-Sierra,Inc.
PM5352
S/UNI廬-155-STAR
鈥?Provides a generic 8-bit
microprocessor interface for device
control and register access.
鈥?Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
鈥?Performs flag sequence detection and
insertion.
鈥?Performs CRC-CCITT and CRC-32
FCS generation and validation.
鈥?Performs byte stuffing and destuffing.
鈥?Checks for minimum and maximum
packet lengths.
鈥?Provides a SATURN廬-compatible
Packet-over-SONET POS-PHY Level
2 Interface.
155 Mbit/s ATM and Packet-Over-SONET/SDH Physical Layer Device
FEATURES
鈥?Single channel ATM and Packet-over-
SONET OC-3c (155 Mbit/s) PHY.
鈥?Provides on-chip clock and data
recovery and clock synthesis.
鈥?Exceeds Bellcore-GR-253 jitter
requirements.
鈥?Inserts and extracts ATM cells or POS
packets into/from SONET SPE.
鈥?Filters and captures Automatic
Protection Switch byes (K1 and K2)
and detects APS byte failure.
鈥?Detects signal degrade and signal
failure thresholds crossing alarms.
鈥?Captures and debounces
synchronization status byte (S1).
鈥?Extracts and inserts the 16 or 64-byte
section trace (J0) and path trace (J1)
messages.
鈥?Extracts and inserts section/line data
communication channels (DCC).
鈥?Provides circuitry to meet holdover,
wander and long term stability.
ATM
鈥?Implements the ATM Forum User
Network Interface Specification.
鈥?Performs cell payload scrambling and
descrambling.
鈥?Provides a UTOPIA Level 2-compliant
system interface.
鈥?Provides synchronous cell transmit
and receive FIFO buffers.
PACKAGING
鈥?Low power, 3.3 V CMOS technology.
鈥?Packaged in a 304-pin Ball Grid Array
(BGA) package.
鈥?Industrial temperature range (-40擄 to
+85擄C).
PACKET-OVER-SONET
鈥?Generic design that supports packet-
based protocols like PPP, HDLC and
Frame Relay.
鈥?Implements the PPP over SONET/
SDH specification according to RFC
2615 and 1662 of the IETF.
APPLICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
DSLAM uplinks.
Access concentrators.
Layer 3 switches.
ATM switches.
BLOCK DIAGRAM
TSDCLK
TFPI
TFPO
TCLK
TSD
TLD
TLDCLK
TXC+
TXC-
TXD+
TXD-
Section
DCC
Insert
Transmit
Section O/H
Processor
Line
DCC
Insert
Transmit
Line O/H
Processor
Transmit
Path O/H
Processor
TMOD
TERR
TEOP
Transmit
ATM Cell
Processor
Transmit
Line
Interface
WAN
Synchronization
DTCA/DTPA
TDAT[15:0]
TPRTY
TSOC/TSOP
TCA
TADR
TENB
TFCLK
PHY_OEN
RFCLK
RENB
RADR
RCA/RVAL
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA/DRP
Transmit
POS Frame
Processor
Section Trace
Buffer
Path Trace
Buffer
Receive
POS Frame
Processor
Receive
Line O/H
Processor
Line
DCC
Extract
Receive
Path O/H
Processor
Receive
APS, Sync,
BERM
Receive
ATM Cell
Processor
ATB[3:0]
REFCLK
RXD+
RXD-
SD
UTOPIA
Level 2 /
POS-PHY
Level 2
System
Interface
Receive
Line
Interface
CP
CN
Receive
Section O/H
Processor
Section
DCC
Extract
REOP
RERR
RMOD
JTAG
Test Access
Port
Microprocessor
Interface
RSD
RSDCLK
RLDCLK
RALRM
RFPO
RCLK
WRB
RDB
ALE
CSB
RLD
TCK
TRSTB
D [7:0]
A [10:0]
RSTB
PMC-991722 (r1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS鈥?INTERNAL USE漏
Copyright PMC-Sierra, Inc. 2000
INTB
TDO
TDI
TMS
1
2
